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LS_3VX2

Summary

LS_3VX2
community
efabless engineering
Hard IP
180nm
efabless
X-FAB
EFXH018A

Licensing

N/A
N/A

Maturity

layout
65

Library Package

8.0
May 21, 2018

Certifications

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Description

Digital level shifter between a 1.8V domain and a 3.3V domain. Matches the row height of digital standard cell set D_CELLS_3V.

Features

  • Matches the footprint of digital standard cell set D_CELLS_3V.

Figure(s)

Pins

NAME DESCRIPTION TYPE DIRECTION VMIN VMAX
A Low-voltage input signal input -0.5 VDD1V8 + 0.3
Q High-voltage output signal output -0.5 VDD3V3 + 0.3
VDD3V3 High-voltage supply power inout +3.0 +3.6
VDD1V8 Low-voltage supply power inout +1.5 +2.1
VSSA Common ground ground inout

Parameters

Global Conditions

NAME MINIMUM TYPICAL MAXIMUM UNITS
VDD3V3 3.3 V
VDD1V8 1.8 V
Ground 0 V
RLoad 100 MΩ
CLoad 1 pF
Temp -40 27 85 °C
Sigma 3
Corner ws tm wp

Electrical Parameters

PARAMETER PIN MINIMUM TYPICAL MAXIMUM UNITS
VOL 4.144e-09 1.921e-08 7.296e-08 V Conditions
VOLTAGE:VDD3V3 3.3 V
VOLTAGE:VDD1V8 1.8 V
VOLTAGE:VSSA 0 V
VOLTAGE:A 0.3 V
RESISTANCE:Q 100 MΩ
CAPACITANCE:Q 1 pF
TEMPERATURE -40 27 85 °C
CORNER ws tm wp
SIGMA 3
VOH 3.3 3.3 3.3 V Conditions
VOLTAGE:VDD3V3 3.3 V
VOLTAGE:VDD1V8 1.8 V
VOLTAGE:VSSA 0 V
VOLTAGE:A 1.5 V
RESISTANCE:Q 100 MΩ
CAPACITANCE:Q 1 pF
TEMPERATURE -40 27 85 °C
CORNER ws tm wp
SIGMA 3
TPD rise @ 3σ 1.396 1.761 2.033 ns Conditions
VOLTAGE:VDD3V3 3.3 V
VOLTAGE:VDD1V8 1.8 V
VOLTAGE:VSSA 0 V
RESISTANCE:Q 100 MΩ
CAPACITANCE:Q 1 pF
TEMPERATURE -40 85 °C
CORNER ws tm wp
SIGMA 3
TPD rise @ 6σ 1.355 1.908 2.747 ns Conditions
VOLTAGE:VDD3V3 3.3 V
VOLTAGE:VDD1V8 1.8 V
VOLTAGE:VSSA 0 V
RESISTANCE:Q 100 MΩ
CAPACITANCE:Q 1 pF
TEMPERATURE -40 85 °C
CORNER ws tm wp
SIGMA 6
TPD fall @ 3σ 1.609 1.968 2.389 ns Conditions
VOLTAGE:VDD3V3 3.3 V
VOLTAGE:VDD1V8 1.8 V
VOLTAGE:VSSA 0 V
RESISTANCE:Q 100 MΩ
CAPACITANCE:Q 1 pF
TEMPERATURE -40 85 °C
CORNER ws tm wp
SIGMA 3
TPD fall @ 6σ 1.426 1.997 2.713 ns Conditions
VOLTAGE:VDD3V3 3.3 V
VOLTAGE:VDD1V8 1.8 V
VOLTAGE:VSSA 0 V
VOLTAGE:VDIFF -0.5 V
RESISTANCE:Q 100 MΩ
CAPACITANCE:Q 1 pF
TEMPERATURE -40 85 °C
CORNER ws tm wp
SIGMA 6
IDD (leakage) 21.6 49.19 196.7 pA Conditions
VOLTAGE:VDD3V3 3.3 V
VOLTAGE:VDD1V8 1.8 V
VOLTAGE:VSSA 0 V
VOLTAGE:A 0.0 1.8 V
RESISTANCE:Q 100 MΩ
CAPACITANCE:Q 1 pF
TEMPERATURE -40 27 85 °C
CORNER ws tm wp
SIGMA 3

Physical Parameters

PARAMETER MINIMUM TYPICAL MAXIMUM UNITS
device_area 113 µm²
area 56.56 µm²
width 9.82 µm
height 5.76 µm
LVS_errors 0
DRC_errors 0

Performance Characteristics

Propagation delay vs. supply voltage VDD3V3