profiles search for area of expertise: Digital: RTL
192 results
Kranthi Kumar Pamarthi
I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.
SKILLS
Mauricio De Carvalho
SKILLS
- C/C++ | Cadence Encounter | Software Developer | System Verilog | Verilog | VHDL |
Praneeth
SKILLS
- Cadence Encounter | Cadence Virtuoso | Hercules | Perl | Spectre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
dongxu yong
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Matlab | Verilog |
AREA OF EXPERTISE
Djamel DELLAA
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Eagle CAD | SPICE Opus | Verilog | VHDL |
AREA OF EXPERTISE
John Sully
SKILLS
- C/C++ | Software Developer | System Verilog | Verilog |
AREA OF EXPERTISE
Jonathan Richard Robert Kimmitt
Research Associate at University of Cambridge
SKILLS
- Verilog |
AREA OF EXPERTISE
Venkata Nitheesh Kumar Reddy Kethu
AREA OF EXPERTISE
Sebastien Riou
SKILLS
- C/C++ | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Mohammed Essam Abd El Samee Soliman
I works as junior physical design engineer and I have passion in VLSI field specially in digital IC design. I have experience in writing RTL, test benches and in PnR flow.
AREA OF EXPERTISE
Eduardo Augusto da Costa
Eduardo is an Electrical Engineer engaged in hardware development with a true passion for developing and enhancing
applications. While at university, he worked in a variety of projects, from VHDL in a SOC project, to a PCB for a power circuit, and even web interfaces for electronic devices network connected. He allies his technical background with great communication skills. He is used to and is passionate about working in diverse cultural environment as was his period as an international student in Japan. He also got a certification in in Digital Integrated Circuit Design and Project Flow with Cadence tools (IC Brazil Program). Currently he works at HT Micron, and is interested in positions related to chip design, hardware design, embedded software development and similar areas.
SKILLS
- C/C++ | Cadence Encounter | Eagle CAD | Matlab | Octave | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Vachan U Bharadwaj
A recent graduate student from Syracuse University major in Electrical Engineering with focus in VLSI Designs
SKILLS
- Cadence Encounter | Cadence Virtuoso | Eagle CAD | Perl | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Anna Mikhteeva
SKILLS
AREA OF EXPERTISE
Peter Atkinson
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Ronan BARZIC
Principal Engineer at ONiO AS
AREA OF EXPERTISE
Alexey Shabalovskiy
Expert in embedded and mobile applications since 2003. Has many years of experience in software and hardware development, effective team management. Excellent in the research and development, technology findings and implementations.
SKILLS
- C/C++ | Leadership | Perl | Python | Software Developer | System-C |
piyush gaur
i am currently persuing mtech from in vlsi design from DTU india.
SKILLS
AREA OF EXPERTISE
Per Magnus Østhus
AREA OF EXPERTISE
Stephan Ahles
SKILLS
- C/C++ | Cadence Virtuoso | Eldo | Electric CAD | Leadership | Matlab | ngspice | Octave | Python | SKILL | Spectre | Verilog | VHDL |
Vincent Trudel-Lapierre
AREA OF EXPERTISE
Tim Whitfield
SKILLS
- Verilog |
AREA OF EXPERTISE
Ben Marshall
SKILLS
- C/C++ | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Menaka Sajjan
SKILLS
- Cadence Encounter | Cadence Virtuoso | Perl | Verilog | VHDL |
AREA OF EXPERTISE
Shilpa Prabhu
VLSI Design Engineer
SKILLS
- Cadence Encounter | Cadence Virtuoso | Verilog | VHDL |
AREA OF EXPERTISE
Emre Goncu
SKILLS
- Cadence Encounter | Cadence Virtuoso | Matlab | Verilog | VHDL |
AREA OF EXPERTISE
Vishal Prafulkumar Katigar
Trained in ASIC verification from Maven silicon Bengaluru
Also having experience in embedded domain (PCB layout design)
SKILLS
- C/C++ | Perl | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Ankit Agrawal
I am VLSI Design & Verification Engineer.
SKILLS
- Aldec RivieraPro | C/C++ | Digital Electronics | System Verilog | UVM | Verilog | Xilinx ISE |
AREA OF EXPERTISE
Ira Chayut
AREA OF EXPERTISE
Pablo Cayuela
SKILLS
- C/C++ | Electric CAD | Matlab | Octave | Scilab | Tanner L-Edit | Verilog | VHDL |
AREA OF EXPERTISE
Nanditha Rao
SKILLS
- Cadence Encounter | Leadership | Magic CAD | ngspice | Verilog |
AREA OF EXPERTISE
Saroj Rout
Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.
SKILLS
AREA OF EXPERTISE
- Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | CAD: Scripting | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | SoC: ESD | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Semiu A. Olowogemo
AREA OF EXPERTISE
Mohamed Salem Abdelgalil
AREA OF EXPERTISE
yalcin balcioglu
SKILLS
AREA OF EXPERTISE
KARIM
ASIC Designer
SKILLS
AREA OF EXPERTISE
Rejoy Roy Mathews
SKILLS
- C/C++ | Cadence Encounter | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Manoj S
Tech Lead
AREA OF EXPERTISE
harikrishna
Physical Design Engineer
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Rifat Demircioglu
Managing Partner
SKILLS
- C/C++ | Leadership | Matlab | Perl | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Syed Asad Alam
Post-doctoral research fellow in the discipline of Software and Systems, School of Computer Science and Statistics, Trinity College Dublin, with a keen interest in learning new things, specially related to computer science and engineering.
Around 4 years experience of teaching and research and more than 10 years of experience in architecture design, optimization, analysis, implementation and verification of digital and digital signal processing systems on FPGAs and ASICs. Diversifying research career by working on quantization of deep convolution neural networks. Author of three peer reviewed journal publications and five international conference publications.
AREA OF EXPERTISE
Alcides Silveira Costa
AREA OF EXPERTISE
Shyam K
AREA OF EXPERTISE
Gordon Aplin
IC Design Engineer
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Magic CAD | ngspice | Perl | Tanner L-Edit | Verilog | VHDL |
AREA OF EXPERTISE
Sumanta
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | System-C | Verilog |
AREA OF EXPERTISE
J. Rodriguez
Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.
SKILLS
- C/C++ | System Verilog | System-C | VHDL |
AREA OF EXPERTISE
Devdatt Haldipur
SKILLS
AREA OF EXPERTISE
Judd Jenne
SKILLS
- C/C++ | Calibre | Python | Software Developer | System Verilog | Tanner L-Edit | Verilog |
AREA OF EXPERTISE
harshitha yadavalli
SKILLS
- Cadence Virtuoso | System-C | Verilog |
AREA OF EXPERTISE
Chaitanya Parashar
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Mohammed Zakir Hussain
SKILLS
- Cadence Encounter | Cadence Virtuoso | Magic CAD | Netgen | ngspice | Spectre | Tanner L-Edit | Verilog | VHDL |
AREA OF EXPERTISE
Shahbaz Abbasi
Design engineer with combined R&D and industrial experience in developing analog/mixed signal ICs for applications including inductive position sensors and imager readouts. Proven abilities with widely used blocks including (but not limited to) filter, amplifier, ADC, DAC, voltage regulators, bandgap reference, ring/LC oscillator, comparator and custom digital logic circuitry. Experience with full tape-out flow including schematic design, analog/mixed-signal simulations, floor planning, layout, system-level verification and chip measurements. Strong familiarity with industry standard tools and instruments used for design, verification and testing such as Cadence, Synopsys, Mentor Graphics, and Keysight. Frontend digital hardware design (ASIC/FPGA) experience using Verilog HDL. Considerable exposure to ASIC backend flow (synthesis and PnR) using Synopsys Design Compiler and Cadence Innovus. Skilled with programming platforms such as MATLAB, C++, C#, Perl, UNIX Shell and VB. Strong education with Ph.D. and MSc. degrees in Electronics Engineering along with several peer-reviewed articles in IEEE journals.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Perl | Python | Scilab | Software Developer | Spectre | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Filters | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB | System: Test Equipment | System: Test Programming |
Dejan Mirkovic
Electronics Engineer and Researcher with a demonstrated history of working in the higher education industry. Skilled in CAD/EDA tools for ASIC, PCB and FPGA design, scripting and programming. Education professional with a PhD in Electrical Engineering and Computer Science from University of Nis, Faculty of Electronic Engineering Nis, Serbia.
SKILLS
AREA OF EXPERTISE
Guy Hutchison
ASIC Designer and entrepreneur
SKILLS
- C/C++ | Leadership | Python | Verilog | chisel |
AREA OF EXPERTISE
Ahmed Ramzy
SKILLS
- C/C++ | Octave | System Verilog | Tanner L-Edit | Verilog | VHDL | ICC | DC |
AREA OF EXPERTISE
Sajal Goyal
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Igor Danilov
SKILLS
- Cadence Encounter | Cadence Virtuoso | Python | Spectre | System Verilog | Tcl/Tk |
AREA OF EXPERTISE
Luc Wong
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Lakshya Kailkhura
SKILLS
AREA OF EXPERTISE
Vincent Pinon
SKILLS
Shuvadeep Kumar
SKILLS
AREA OF EXPERTISE
pranay reddy
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Verilog |
AREA OF EXPERTISE
Anton Babushkin
SKILLS
- Verilog |
AREA OF EXPERTISE
James Tandon
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Eagle CAD | Eldo | Leadership | Magic CAD | Matlab | Octave | Perl | Python | Scilab | Software Developer | System Verilog | Verilog |
AREA OF EXPERTISE
Asier Goikoetxea
SKILLS
- C/C++ | System Verilog | Verilog |
AREA OF EXPERTISE
KADAR A A
I am researcher with goals of developing high end technologies for the future.
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Eldo | Leadership | Matlab | ngspice | Tanner L-Edit | Verilog | VHDL |
AREA OF EXPERTISE
Dave Cameron
SKILLS
- C/C++ | Magic CAD | Python | Software Developer | System Verilog | Verilog |
AREA OF EXPERTISE
Laurent Lamesch
HW development engineer
AREA OF EXPERTISE
- Analog: Design | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Test Equipment |
JON MUNOA
AREA OF EXPERTISE
Marcus N
System and database administrator, embedded systems hobbyist.
AREA OF EXPERTISE
eldho george
SKILLS
- Cadence Virtuoso | Matlab | Perl | System Verilog | Verilog |
AREA OF EXPERTISE
Yuan Mei
An experimental physicist through sensor and instrumentation development.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Leadership | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |
ABDULLAH RAZA Khan
SKILLS
- C/C++ | Synthesis | Digital design |
AREA OF EXPERTISE
George Duffy
SKILLS
AREA OF EXPERTISE
Bhaskar Moni
VLSI Engineer
SKILLS
- C/C++ | Cadence Virtuoso | Verilog |
AREA OF EXPERTISE
ALAIN POTTECK
VLSI design project manager
SKILLS
AREA OF EXPERTISE
Julio
RTL Engineer
SKILLS
- C/C++ | Matlab | System Verilog | Verilog |
AREA OF EXPERTISE
Yunzhe Li
MS IC Designer, focusing on imager design in deep submicron technologies
AREA OF EXPERTISE
Brian Glod
AREA OF EXPERTISE
- Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Mohammed Nabeel
Learner for life
SKILLS
- Perl | Python | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Mahmoud Youssuf Ahmad
Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Federico Paredes
Digital designer experienced in high-speed ASICs for optical/copper transceivers, including DSPs, error correction and SoC support.
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Python | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
Muhammad Awais Bin Altaf
SKILLS
- Cadence Virtuoso | Calibre | Matlab | Spectre | Verilog |
Marco Merlin
Electronics Engineer with 10 years experience in microelectronics and research.
Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms.
Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to.
During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.
SKILLS
AREA OF EXPERTISE
Caio Alonso da Costa
SKILLS
- C/C++ | Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
AGhani
Associate Professor (Electrical and Electronic Engineering)
Implantable chip design
Low power sensors
SKILLS
- Cadence Encounter | Cadence Virtuoso | Leadership | Matlab | SPICE Opus | Verilog | VHDL |
AREA OF EXPERTISE
Niels Moseley
SKILLS
- C/C++ | Cadence Encounter | DSP | Matlab | Python | Software Developer | Verilog | VHDL |
AREA OF EXPERTISE
Leonel ACUNHA GUIMARAES
SKILLS
- Cadence Virtuoso | Verilog | VHDL |
AREA OF EXPERTISE
Botond Sandor Kirei
AREA OF EXPERTISE
Shimon Hempling
AREA OF EXPERTISE
Yao Ming Kuo
Hardware design engineer
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | Verilog |
AREA OF EXPERTISE
Alfonso Chacon-Rodriguez
Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design.
Fiction writer (National Literature Award for Novel, 2011, Costa Rica)
SKILLS
- Calibre | Eldo | Electric CAD | Matlab | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
ardencaple
Semiconductor professional with 40 years experience.
I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.
AREA OF EXPERTISE
Bharath Shashidhar
SKILLS
AREA OF EXPERTISE
Paulo Roberto Bueno de Carvalho
Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes.
He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.
SKILLS
- C/C++ | Cadence Encounter | Python | System Verilog | Verilog | VHDL |
Hossam Hassan
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming | System: PCB |
Bob Ledzius
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
SKILLS
- C/C++ | Leadership | Matlab | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Business: Design Services | Business: Management | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: PCB |
Ernesto Conde
Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | ngspice | Python | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Hasan Mohamed
AREA OF EXPERTISE
HALIM
Lecturer
UiTM
SKILLS
AREA OF EXPERTISE
Mahmoud Abdelgawad
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Mostafa Elbediwy
Teaching assistant for ASIC/FPGA and digital ICs courses.
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Matlab | System Verilog | Verilog |
AREA OF EXPERTISE
Mostafa El Naggar
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | Verilog |
AREA OF EXPERTISE
Akram Selim
AREA OF EXPERTISE
Netsanet gebeyehu
Analog/RF/Digital design manager
SKILLS
- Cadence Virtuoso | Calibre | Matlab | Verilog |
AREA OF EXPERTISE
Jose Maria Hinojo
SKILLS
- Allegro | Altium | C/C++ | Cadence Assura | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Perl | Tcl/Tk | VHDL |
AREA OF EXPERTISE
Shivam Potdar
RISC-V Enthusiast
GSoC 2020 @ FOSSi Foundation
RA @ CAD Lab, IISc Bengaluru, India
EE Senior @ NITK Mangalore, India
AREA OF EXPERTISE
Denise Cocco
President and CEO
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Matlab | Perl | Python | SKILL | Spectre | SPICE Opus | System Verilog | Tanner L-Edit | Verilog |
AREA OF EXPERTISE
- Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Foundry Services | Business: Packaging | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: Fabrication Process | System: Packaging | System: Quality Assurance |
Vamshidhar Reddy
I am passionate VLSI trainee looking to explore my skills and build few projects which enhance my coding and debugging skills.
SKILLS
- C/C++ | Cadence Virtuoso | Verilog |
AREA OF EXPERTISE
Sreenivasan Jouly
SKILLS
- C/C++ | Matlab | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Ricardo Godinez
AREA OF EXPERTISE
Tung Hoang
R&D Engineer
SKILLS
- Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Arun Jeevaraj
ASIC Developer at Ericsson, trying hands with the open source tool flow.
SKILLS
- C/C++ | System Verilog | System-C |
AREA OF EXPERTISE
kiran guruprasad shetty ps
SKILLS
AREA OF EXPERTISE
Vivek Parmar
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | ngspice | Octave | Python | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |
Geethanand N
Ex intel professional with over 5 years of experience in front end Vlsi
SKILLS
- Perl | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
CHDL Custom High-Speed Digital Logic
We are group of experienced engineers working in Front-End Digital Logic Design.
AREA OF EXPERTISE
Ippei Akita
An analog mixed-signal circuit designer for low-power precision sensor interfaces. See https://staff.aist.go.jp/ippei.akita/
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Python | Spectre | Verilog |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: Chip Editing | System: PCB | System: Test Equipment |
wilfred kisku
PhD Scholar
SKILLS
- System Verilog | System-C | Verilog |
AREA OF EXPERTISE
Ha Tran
SKILLS
- Cadence Virtuoso | Calibre | Python | Verilog |
AREA OF EXPERTISE
Aliaa Fouli
Digital Logic Designer
AREA OF EXPERTISE
Joseph Kiniry
Dad. Partner. Scientist. Activist. Maker. — He/His
SKILLS
- C/C++ | Cadence Virtuoso | Eagle CAD | Leadership | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | Bluespec | Chisel | EDA R&D |
AREA OF EXPERTISE
- Academic: Research | Business: Design Services | Business: Management | CAD: Tool Development | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: Quality Assurance | System: Test Programming | Miscellaneous: Formal Methods |
Stefano
SKILLS
- C/C++ | Matlab | System Verilog | Tcl/Tk |
AREA OF EXPERTISE
Pepijn de Vos
AREA OF EXPERTISE
Shubham Tonde
I am recently completed my post-graduation in VLSI and Embedded system from coep pune(India). I like to work in a backend design of VLSI.
SKILLS
- Digital design | pel | sta | Verilog |
AREA OF EXPERTISE
Rahul Behl
SKILLS
- Perl | Python | System Verilog | Verilog |
AREA OF EXPERTISE
KUMAR SAKET
AREA OF EXPERTISE
Pratika Tripathi
I am Pratika Tripathi. I am in my final year of Btech. I am very interested in physical designing of IC. I had even taken 3 courses of kunal ghosh sir on physical design, stay, and cts.
I am doing my final year project in physical design.
AREA OF EXPERTISE
Pragati Tripathi
SKILLS
- asic | fpga | physical design | Verilog |
AREA OF EXPERTISE
Kiran Prasad Kanaparthi
SKILLS
- C/C++ | Leadership | Perl | Python | System Verilog |
AREA OF EXPERTISE
Hanssel Morales
AREA OF EXPERTISE
RAJESH M
SKILLS
- C/C++ | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Bhuwan Kaushik
AREA OF EXPERTISE
Amit Bachiphale
SKILLS
AREA OF EXPERTISE
Chaitanya CVS
SKILLS
- Perl | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
Mandala Sai Uthej
SKILLS
- Verilog |
AREA OF EXPERTISE
Mehmet Sait Eroğlu
SKILLS
AREA OF EXPERTISE
Guy Hutchison
SKILLS
- Leadership | Python | Verilog |
AREA OF EXPERTISE
ADITYA ANAND
SKILLS
- Cadence Encounter | Matlab | ngspice | Python | System Verilog | Tcl/Tk | Verilog |
Jan Bělohoubek
AREA OF EXPERTISE
Sergey Churayev
SKILLS
- Cadence Encounter | Cadence Virtuoso | Electric CAD | Matlab | ngspice | Octave | Verilog | VHDL |
AREA OF EXPERTISE
Elias Vieira
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | System Verilog | Verilog |
AREA OF EXPERTISE
Anurag Darbari
SubIP and SoC Design Verification Engineer. Extends to running Full Chip Emulation on Palladium and Protium Platforms.
SKILLS
- System Verilog | uvm | Verilog |
AREA OF EXPERTISE
sampath vp
Semiconductor
SKILLS
- Cadence Encounter | Leadership | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Bhagesh Choudhry Maheshwari
ASIC/FPGA Design Engineer | Former Intern in CERN | Former Cultural Ambassador of Pakistan in USA | Gold Medalist
SKILLS
- Matlab |
AREA OF EXPERTISE
Manish Mahajan
I am a design / verification Engineer for ASIC and FPGA .
SKILLS
- C/C++ | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Timothy Linden
SKILLS
- C/C++ | Matlab | Software Developer | VHDL |
AREA OF EXPERTISE
Thomas Parry
Mixed-signal designer
SKILLS
- Cadence Virtuoso | Calibre | Matlab | Netgen | ngspice | Python | Spectre | Tanner L-Edit | Verilog | VHDL |
AREA OF EXPERTISE
Mustafa Khairallah
I am a Ph.D. student at the School of Physical and Mathematical Sciences, NTU, Singapore. I co-designed the Romulus and Remus families of lightweight authenticated encryption modes with Tetsu Iwata, Kazuhiko Minematsu and Thomas Peyrin, which are the basis of three candidates for the NIST Lightweight Cryptography Competition. Previously, I got my BSc. in Electronics Engineering from Alexandria University, Egypt. My main research focus is the practical aspects of Symmetric Key Cryptography, which includes: Physical Security, Hardware Implementations, Practical Cryptanalysis and Primitive Design. Previous research projects also included the acceleration of Fully Homomorphic Encryption and Design and Verification of Digital Circuits.
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL | perl |
AREA OF EXPERTISE
Ken Pettit
Digital Systems and Software Engineer (formerly in management VP and Director of engineering).
SKILLS
- C/C++ | Leadership | Software Developer | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Sanjeev Sreeganesh Sasalu
SKILLS
AREA OF EXPERTISE
Loester Franco Botelho
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Alexander Stanitzki
Analog/MS/RF IC designer
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Diva | Leadership | Python | SKILL | Spectre | Verilog |
Manar Abdelatty
SKILLS
- Verilog |
AREA OF EXPERTISE
Phillip Pearson
AREA OF EXPERTISE
Vladimir Milovanović
SKILLS
AREA OF EXPERTISE
Harrison Pham
SKILLS
- Verilog |
AREA OF EXPERTISE
Gaurav Kumar K
PhD Student, School of Electrical and Computer Engineering, Purdue University, USA.
Research interests include Mixed Signal Circuits, High Speed Circuits and Digital System Design
SKILLS
- C/C++ | Cadence Virtuoso | Eagle CAD | Matlab |
AREA OF EXPERTISE
Elliot Buller
SKILLS
- C/C++ | System Verilog |
AREA OF EXPERTISE
Anton Blanchard
AREA OF EXPERTISE
Lakshana Ramalingam
SKILLS
- Verilog |
AREA OF EXPERTISE
Tore Leikanger
SKILLS
- C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Octave | Python | Software Developer | System Verilog |
AREA OF EXPERTISE
Boobalan Deiveegan
SKILLS
AREA OF EXPERTISE
M. Shalan
AREA OF EXPERTISE
Pavan Sai
I am a final year B.Tech undergrad from India highly passionate about digital system design.
SKILLS
- C/C++ | Leadership | Matlab | Python | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Leonidas Kosmidis
I'm a Senior Researcher at the Barcelona Supercomputing Center and Junior Faculty at Polytechnic University of Catalonia (UPC). I'm the recipient of the RISC-V Educator of the Year Award 2019, for the advanced graduate course Processor Design I'm teaching at UPC, which is focused on the design of high-performance safety-critical systems. I'm the PI of the GPU4S project funded by the European Space Agency (ESA) in which we are investigating the applicability of embedded GPUs in space.
SKILLS
- C/C++ | Electric CAD | Leadership | Software Developer | Verilog |
AREA OF EXPERTISE
Dan Rodrigues
SKILLS
- Verilog |
AREA OF EXPERTISE
Klaus V
Analog mixed signal Asic design
SKILLS
AREA OF EXPERTISE
Sanggun Kim
SKILLS
- C/C++ | python | System Verilog | Verilog |
AREA OF EXPERTISE
vasundhara sanivarapu
SKILLS
AREA OF EXPERTISE
Bill Patterson
AREA OF EXPERTISE
Jeremie Crenne
SKILLS
- C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Joel Sanchez Moreno
My name is Joel Sanchez Moreno I graduated as a Computer engineer and I currently work as a full time RTL design engineer for a start up. In addition, I am doing a part-time master on High Performance Computing on the Universitat Politècnica de Catalunya (UPC)
SKILLS
- Python | System Verilog | Verilog |
AREA OF EXPERTISE
Anthony Kung
Hi, I'm an Electrical & Computer Engineering + Computer Science student at Oregon State University.
SKILLS
- C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Steven Herbst
I'm a PhD student working to make mixed-signal chip design more accessible, drawing inspiration from software development techniques. Prior to starting the PhD program, I spent a number of years working in industry at both the chip- and PCB-level on optical sensors and power systems.
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | Spectre | System Verilog | Verilog |
AREA OF EXPERTISE
Sylvain Munaut
AREA OF EXPERTISE
Zain Rizwan Khan
Research Associate at Micro Electronics Research Lab (MERL) working as a hardware design engineer.
SKILLS
- C/C++ | System Verilog | UVM | Verilog |
AREA OF EXPERTISE
Muhammed Ceylan Morgul
UVA HPLP
Daniel Limbrick
I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.
SKILLS
AREA OF EXPERTISE
Sathyanarayanan
I am accomplished digital design engineer having 8 years of industrial expertise .
I am currently working on IP design and IP integrations stuffs .
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Verilog |
AREA OF EXPERTISE
Ahmed Yiwere
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | ngspice | Perl | Python | System Verilog | Verilog | VHDL |
Aravind V J
AREA OF EXPERTISE
Arthur Fortini
AREA OF EXPERTISE
Furkan Sahin
Senior FPGA Design Engineer
AREA OF EXPERTISE
Yunus Dawji
I am a PhD candidate with analog and digital design experience.