Tag results for: area of expertise

Kranthi Kumar Pamarthi

I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.

SKILLS

Magic CAD | Matlab | Netgen | ngspice | Octave | Python | System Verilog | Tcl/Tk | Verilog | VHDL | perl |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Circuits: Filters | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | System: FPGA Programming |

Mauricio De Carvalho

SKILLS

C/C++ | Cadence Encounter | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Business: Design Services | Circuits: Microcontrollers | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming |

Praneeth

SKILLS

Cadence Encounter | Cadence Virtuoso | Hercules | Perl | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Memory | Circuits: Power Management | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning |

dongxu yong

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Verilog |

AREA OF EXPERTISE

Analog: Design | Digital: RTL |

Djamel DELLAA

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Eagle CAD | SPICE Opus | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Verification | Digital: RTL | Digital: Synthesis |

John Sully

SKILLS

C/C++ | Software Developer | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Jonathan Richard Robert Kimmitt

Research Associate at University of Cambridge

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Venkata Nitheesh Kumar Reddy Kethu

SKILLS

C/C++ | Eagle CAD | Matlab | Octave | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Circuits: Filters | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Sebastien Riou

SKILLS

C/C++ | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | Miscellaneous: Cryptography |

Mohammed Essam Abd El Samee Soliman

I works as junior physical design engineer and I have passion in VLSI field specially in digital IC design. I have experience in writing RTL, test benches and in PnR flow.

SKILLS

Leadership | Matlab | Perl | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Eduardo Augusto da Costa

Eduardo is an Electrical Engineer engaged in hardware development with a true passion for developing and enhancing applications. While at university, he worked in a variety of projects, from VHDL in a SOC project, to a PCB for a power circuit, and even web interfaces for electronic devices network connected. He allies his technical background with great communication skills. He is used to and is passionate about working in diverse cultural environment as was his period as an international student in Japan. He also got a certification in in Digital Integrated Circuit Design and Project Flow with Cadence tools (IC Brazil Program). Currently he works at HT Micron, and is interested in positions related to chip design, hardware design, embedded software development and similar areas.

SKILLS

C/C++ | Cadence Encounter | Eagle CAD | Matlab | Octave | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Vachan U Bharadwaj

A recent graduate student from Syracuse University major in Electrical Engineering with focus in VLSI Designs

SKILLS

Cadence Encounter | Cadence Virtuoso | Eagle CAD | Perl | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: PCB | System: Signal Integrity |

Anna Mikhteeva

SKILLS

Analog/Digital Circuit Design | C/C++ |

AREA OF EXPERTISE

Analog-Mixed Signal-DV | Digital: RTL |

Peter Atkinson

SKILLS

C/C++ | Cadence Encounter | Matlab | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Ronan BARZIC

Principal Engineer at ONiO AS

SKILLS

C/C++ | Magic CAD | ngspice | Python | System-C | Verilog |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Power Management | Digital: RTL | Digital: Verification | Miscellaneous: Neural Networks | SoC: Verification |

Alexey Shabalovskiy

Expert in embedded and mobile applications since 2003. Has many years of experience in software and hardware development, effective team management. Excellent in the research and development, technology findings and implementations.

SKILLS

C/C++ | Leadership | Perl | Python | Software Developer | System-C |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Business: Design Services | Business: Management | CAD: Scripting | CAD: Tool Development | Circuits: Communication | Circuits: Microcontrollers | Digital: RTL | System: PCB | System: Quality Assurance | System: Test Programming |

piyush gaur

i am currently persuing mtech from in vlsi design from DTU india.

SKILLS

Verilog | cmos integrated circuit |

AREA OF EXPERTISE

Digital: RTL |

Per Magnus Østhus

SKILLS

C/C++ | Perl | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis |

Stephan Ahles

SKILLS

C/C++ | Cadence Virtuoso | Eldo | Electric CAD | Leadership | Matlab | ngspice | Octave | Python | SKILL | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Marketing | Business: Sales | CAD: Scripting | Circuits: Communication | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis |

Bill Flynn

SKILLS

C/C++ | Perl | Python | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Vincent Trudel-Lapierre

SKILLS

C/C++ | Matlab | Octave | Python | Scilab | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | Miscellaneous: Cryptography | Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Test Equipment |

Tim Whitfield

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

Ben Marshall

SKILLS

C/C++ | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Circuits: Microcontrollers | Digital: RTL | Digital: Verification | Miscellaneous: Cryptography |

Menaka Sajjan

SKILLS

Cadence Encounter | Cadence Virtuoso | Perl | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: ESD |

Shilpa Prabhu

VLSI Design Engineer

SKILLS

Cadence Encounter | Cadence Virtuoso | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Emre Goncu

SKILLS

Cadence Encounter | Cadence Virtuoso | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Vishal Prafulkumar Katigar

Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)

SKILLS

C/C++ | Perl | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers | Circuits: Sensors | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: PCB |

Ankit Agrawal

I am VLSI Design & Verification Engineer.

SKILLS

Aldec RivieraPro | C/C++ | Digital Electronics | System Verilog | UVM | Verilog | Xilinx ISE |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | SoC: Verification |

Ira Chayut

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | SoC: Verification |

Pablo Cayuela

SKILLS

C/C++ | Electric CAD | Matlab | Octave | Scilab | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Digital: RTL | System: FPGA Programming |

Nanditha Rao

SKILLS

Cadence Encounter | Leadership | Magic CAD | ngspice | Verilog |

AREA OF EXPERTISE

Academic: Teaching | Digital: RTL | System: FPGA Programming | System: Signal Integrity |

Saroj Rout

Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.

SKILLS

Calibre | Eagle CAD | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Scilab | SKILL | Spectre | System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | CAD: Scripting | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | SoC: ESD | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Semiu A. Olowogemo

SKILLS

C/C++ | Cadence Virtuoso | Perl | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Mohamed Salem Abdelgalil

SKILLS

Perl | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | System: FPGA Programming |

yalcin balcioglu

SKILLS

System Verilog |

AREA OF EXPERTISE

Digital: RTL |

KARIM

ASIC Designer

SKILLS

Digital ASIC design |

AREA OF EXPERTISE

Digital: RTL |

Rejoy Roy Mathews

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Digital: RTL |

Manoj S

Tech Lead

SKILLS

C/C++ | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | System: FPGA Programming |

harikrishna

Physical Design Engineer

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Rifat Demircioglu

Managing Partner

SKILLS

C/C++ | Leadership | Matlab | Perl | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Business: Design Services | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Syed Asad Alam

Post-doctoral research fellow in the discipline of Software and Systems, School of Computer Science and Statistics, Trinity College Dublin, with a keen interest in learning new things, specially related to computer science and engineering. Around 4 years experience of teaching and research and more than 10 years of experience in architecture design, optimization, analysis, implementation and verification of digital and digital signal processing systems on FPGAs and ASICs. Diversifying research career by working on quantization of deep convolution neural networks. Author of three peer reviewed journal publications and five international conference publications.

SKILLS

C/C++ | Matlab | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | System: FPGA Programming |

Alcides Silveira Costa

SKILLS

C/C++ | Leadership | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | CAD: Scripting | CAD: Tool Development | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Shyam K

SKILLS

Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Gordon Aplin

IC Design Engineer

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Magic CAD | ngspice | Perl | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Sumanta

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | Digital: Verification | System: FPGA Programming |

J. Rodriguez

Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.

SKILLS

C/C++ | System Verilog | System-C | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Devdatt Haldipur

SKILLS

Tanner L-Edit |

AREA OF EXPERTISE

Digital: RTL |

Judd Jenne

SKILLS

C/C++ | Calibre | Python | Software Developer | System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | System: FPGA Programming |

harshitha yadavalli

SKILLS

Cadence Virtuoso | System-C | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Simulation | Digital: RTL | SoC: ESD |

Chaitanya Parashar

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | SoC: Verification |

Mohammed Zakir Hussain

SKILLS

Cadence Encounter | Cadence Virtuoso | Magic CAD | Netgen | ngspice | Spectre | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Teaching | Digital: RTL | Digital: Synthesis |

Shahbaz Abbasi

Design engineer with combined R&D and industrial experience in developing analog/mixed signal ICs for applications including inductive position sensors and imager readouts. Proven abilities with widely used blocks including (but not limited to) filter, amplifier, ADC, DAC, voltage regulators, bandgap reference, ring/LC oscillator, comparator and custom digital logic circuitry. Experience with full tape-out flow including schematic design, analog/mixed-signal simulations, floor planning, layout, system-level verification and chip measurements. Strong familiarity with industry standard tools and instruments used for design, verification and testing such as Cadence, Synopsys, Mentor Graphics, and Keysight. Frontend digital hardware design (ASIC/FPGA) experience using Verilog HDL. Considerable exposure to ASIC backend flow (synthesis and PnR) using Synopsys Design Compiler and Cadence Innovus. Skilled with programming platforms such as MATLAB, C++, C#, Perl, UNIX Shell and VB. Strong education with Ph.D. and MSc. degrees in Electronics Engineering along with several peer-reviewed articles in IEEE journals.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Perl | Python | Scilab | Software Developer | Spectre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Filters | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB | System: Test Equipment | System: Test Programming |

Dejan Mirkovic

Electronics Engineer and Researcher with a demonstrated history of working in the higher education industry. Skilled in CAD/EDA tools for ASIC, PCB and FPGA design, scripting and programming. Education professional with a PhD in Electrical Engineering and Computer Science from University of Nis, Faculty of Electronic Engineering Nis, Serbia.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Matlab | Octave | Python | SKILL | Spectre | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | CAD: Scripting | Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB |

Guy Hutchison

ASIC Designer and entrepreneur

SKILLS

C/C++ | Leadership | Python | Verilog | chisel |

AREA OF EXPERTISE

Digital: RTL | Miscellaneous: Cryptography |

Ahmed Ramzy

SKILLS

C/C++ | Octave | System Verilog | Tanner L-Edit | Verilog | VHDL | ICC | DC |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Sajal Goyal

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | SoC: Verification |

Igor Danilov

SKILLS

Cadence Encounter | Cadence Virtuoso | Python | Spectre | System Verilog | Tcl/Tk |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | CAD: Scripting | Digital: RTL | Digital: Synthesis | Digital: Verification |

Luc Wong

I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Lakshya Kailkhura

SKILLS

Cadence Encounter |

AREA OF EXPERTISE

CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: ESD | SoC: Floorplanning | System: Signal Integrity |

Vincent Pinon

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Octave | Perl | Python | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | Circuits: Communication | Circuits: Power Management | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | System: Test Programming |

Shuvadeep Kumar

SKILLS

Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Circuits: Memory | Digital: RTL |

pranay reddy

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification |

Anton Babushkin

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

James Tandon

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eagle CAD | Eldo | Leadership | Magic CAD | Matlab | Octave | Perl | Python | Scilab | Software Developer | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Business: Design Services | CAD: Tool Development | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: Chip Editing | System: FPGA Programming | System: PCB |

Asier Goikoetxea

SKILLS

C/C++ | System Verilog | Verilog |

AREA OF EXPERTISE

Business: Design Services | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography |

KADAR A A

I am researcher with goals of developing high end technologies for the future.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Leadership | Matlab | ngspice | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Digital: RTL | System: FPGA Programming |

Edab

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Perl | Python | Software Developer | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | CAD: Scripting | Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Miscellaneous: Neural Networks | System: FPGA Programming |

Dave Cameron

SKILLS

C/C++ | Magic CAD | Python | Software Developer | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | System: PCB |

Laurent Lamesch

HW development engineer

SKILLS

C/C++ | Eagle CAD | Matlab | Octave | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Test Equipment |

JON MUNOA

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis |

Marcus N

System and database administrator, embedded systems hobbyist.

SKILLS

C/C++ | Perl | Python | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | System: FPGA Programming |

eldho george

SKILLS

Cadence Virtuoso | Matlab | Perl | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | SoC: Verification |

Yuan Mei

An experimental physicist through sensor and instrumentation development.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Leadership | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |

ABDULLAH RAZA Khan

SKILLS

C/C++ | Synthesis | Digital design |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | Digital: Verification |

George Duffy

SKILLS

System Verilog |

AREA OF EXPERTISE

Digital: RTL |

Bhaskar Moni

VLSI Engineer

SKILLS

C/C++ | Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification |

ALAIN POTTECK

VLSI design project manager

SKILLS

Cadence Encounter | Cadence Virtuoso | Spectre | Verilog |

AREA OF EXPERTISE

Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Julio

RTL Engineer

SKILLS

C/C++ | Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Mikhail

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

Yunzhe Li

MS IC Designer, focusing on imager design in deep submicron technologies

SKILLS

Cadence Virtuoso | Calibre | Diva | SKILL | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Sensors | Digital: RTL | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment |

Brian Glod

SKILLS

C/C++ | Eagle CAD | Python | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Mohammed Nabeel

Learner for life

SKILLS

Perl | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | System: FPGA Programming |

Mahmoud Youssuf Ahmad

Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: FPGA Programming |

Federico Paredes

Digital designer experienced in high-speed ASICs for optical/copper transceivers, including DSPs, error correction and SoC support.

SKILLS

C/C++ | Cadence Encounter | Matlab | Octave | Python | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Communication | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Muhammad Awais Bin Altaf

SKILLS

Cadence Virtuoso | Calibre | Matlab | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Marco Merlin

Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Octave | Python | SKILL | System Verilog | Verilog | VHDL | wifi | bluetooth | LTE |

AREA OF EXPERTISE

Analog: Verification | Circuits: Communication | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Neural Networks | SoC: Verification | System: PCB | System: Test Equipment | System: Test Programming |

Caio Alonso da Costa

SKILLS

C/C++ | Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | Digital: Verification |

AGhani

Associate Professor (Electrical and Electronic Engineering) Implantable chip design Low power sensors

SKILLS

Cadence Encounter | Cadence Virtuoso | Leadership | Matlab | SPICE Opus | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Sensors | Digital: Placement and Routing | Digital: RTL | System: Chip Editing | System: FPGA Programming |

Niels Moseley

SKILLS

C/C++ | Cadence Encounter | DSP | Matlab | Python | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | System: FPGA Programming |

Leonel ACUNHA GUIMARAES

SKILLS

Cadence Virtuoso | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Layout | CAD: Tool Development | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: Test Programming |

Botond Sandor Kirei

SKILLS

C/C++ | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Circuits: Filters | Circuits: Signal Processing | Digital: RTL |

Shimon Hempling

SKILLS

Magic CAD | Python | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Yao Ming Kuo

Hardware design engineer

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Alfonso Chacon-Rodriguez

Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design. Fiction writer (National Literature Award for Novel, 2011, Costa Rica)

SKILLS

Calibre | Eldo | Electric CAD | Matlab | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

ardencaple

Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.

SKILLS

C/C++ | Leadership | Python | Verilog | VHDL | DC | PrimeTime |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: Fabrication Process | System: FPGA Programming | Digital audio | IoT | Soc | Mixed Signal |

Bharath Shashidhar

SKILLS

System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Paulo Roberto Bueno de Carvalho

Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: FPGA Programming | System: PCB |

Hossam Hassan

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming | System: PCB |

Bob Ledzius

35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.

SKILLS

C/C++ | Leadership | Matlab | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Business: Design Services | Business: Management | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: PCB |

Ernesto Conde

Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | ngspice | Python | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Hasan Mohamed

SKILLS

C/C++ | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Digital: RTL | Digital: Synthesis | Miscellaneous: Neural Networks | System: FPGA Programming |

HALIM

Lecturer UiTM

SKILLS

System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Academic: Teaching | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning |

Mahmoud Abdelgawad

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Digital: DFT | Digital: RTL | Digital: Synthesis | Digital: Verification |

Mostafa Elbediwy

Teaching assistant for ASIC/FPGA and digital ICs courses.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Mostafa El Naggar

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Digital: RTL | Digital: Synthesis |

Akram Selim

SKILLS

Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Netsanet gebeyehu

Analog/RF/Digital design manager

SKILLS

Cadence Virtuoso | Calibre | Matlab | Verilog |

AREA OF EXPERTISE

Analog: Design | Digital: RTL |

Jose Maria Hinojo

SKILLS

Allegro | Altium | C/C++ | Cadence Assura | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Perl | Tcl/Tk | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: Chip Editing |

Shivam Potdar

RISC-V Enthusiast GSoC 2020 @ FOSSi Foundation RA @ CAD Lab, IISc Bengaluru, India EE Senior @ NITK Mangalore, India

SKILLS

C/C++ | Eagle CAD | Matlab | ngspice | System Verilog | Verilog | c |

AREA OF EXPERTISE

Academic: Student | CAD: Scripting | Digital: RTL | Miscellaneous: Neural Networks | SoC: ESD | System: FPGA Programming |

Denise Cocco

President and CEO

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Matlab | Perl | Python | SKILL | Spectre | SPICE Opus | System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Foundry Services | Business: Packaging | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: Fabrication Process | System: Packaging | System: Quality Assurance |

Vamshidhar Reddy

I am passionate VLSI trainee looking to explore my skills and build few projects which enhance my coding and debugging skills.

SKILLS

C/C++ | Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | Digital: Synthesis |

Sreenivasan Jouly

SKILLS

C/C++ | Matlab | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Ricardo Godinez

SKILLS

Python | Tcl/Tk | Verilog | DFT |

AREA OF EXPERTISE

Digital: DFT | Digital: RTL |

Tung Hoang

R&D Engineer

SKILLS

Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: Floorplanning |

Arun Jeevaraj

ASIC Developer at Ericsson, trying hands with the open source tool flow.

SKILLS

C/C++ | System Verilog | System-C |

AREA OF EXPERTISE

Digital: RTL |

kiran guruprasad shetty ps

SKILLS

Cadence Virtuoso |

AREA OF EXPERTISE

Digital: RTL |

Vivek Parmar

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | ngspice | Octave | Python | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Modeling | Analog: Simulation | Circuits: Memory | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Test Equipment |

Geethanand N

Ex intel professional with over 5 years of experience in front end Vlsi

SKILLS

Perl | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

CAD: Scripting | Digital: RTL | Digital: Verification | SoC: Verification |

CHDL Custom High-Speed Digital Logic

We are group of experienced engineers working in Front-End Digital Logic Design.

SKILLS

Verilog | VHDL | MIPI | C-PHY | D-PHY |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis |

Ippei Akita

An analog mixed-signal circuit designer for low-power precision sensor interfaces. See https://staff.aist.go.jp/ippei.akita/

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Python | Spectre | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: Chip Editing | System: PCB | System: Test Equipment |

wilfred kisku

PhD Scholar

SKILLS

System Verilog | System-C | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis |

Ha Tran

SKILLS

Cadence Virtuoso | Calibre | Python | Verilog |

AREA OF EXPERTISE

Analog: Design | Circuits: Memory | Digital: RTL |

Aliaa Fouli

Digital Logic Designer

SKILLS

Python | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Joseph Kiniry

Dad. Partner. Scientist. Activist. Maker. — He/His

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Leadership | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | Bluespec | Chisel | EDA R&D |

AREA OF EXPERTISE

Academic: Research | Business: Design Services | Business: Management | CAD: Tool Development | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: Quality Assurance | System: Test Programming | Miscellaneous: Formal Methods |

Stefano

SKILLS

C/C++ | Matlab | System Verilog | Tcl/Tk |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Pepijn de Vos

SKILLS

C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | Spectre | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Digital: RTL | Digital: Synthesis |

Shubham Tonde

I am recently completed my post-graduation in VLSI and Embedded system from coep pune(India). I like to work in a backend design of VLSI.

SKILLS

Digital design | pel | sta | Verilog |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL |

Rahul Behl

SKILLS

Perl | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification |

KUMAR SAKET

SKILLS

C/C++ | Python | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis |

Pratika Tripathi

I am Pratika Tripathi. I am in my final year of Btech. I am very interested in physical designing of IC. I had even taken 3 courses of kunal ghosh sir on physical design, stay, and cts. I am doing my final year project in physical design.

SKILLS

veilog | vhdl | asic flow | physical design | sta | fpga | vlsi |

AREA OF EXPERTISE

Academic: Research | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: Fabrication Process | System: FPGA Programming | System: Packaging |

Pragati Tripathi

SKILLS

asic | fpga | physical design | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL |

Kiran Prasad Kanaparthi

SKILLS

C/C++ | Leadership | Perl | Python | System Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | Digital: Verification |

Hanssel Morales

SKILLS

C/C++ | Cadence Encounter | Chisel | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification |

RAJESH M

SKILLS

C/C++ | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Bhuwan Kaushik

SKILLS

C/C++ | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Amit Bachiphale

SKILLS

System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | Digital: Verification |

Chaitanya CVS

SKILLS

Perl | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research | CAD: Scripting | CAD: Tool Development | Digital: DFT | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming |

Mandala Sai Uthej

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: ESD | SoC: Floorplanning | System: Signal Integrity |

Mehmet Sait Eroğlu

SKILLS

System Verilog | Synopsys |

AREA OF EXPERTISE

Digital: RTL |

Guy Hutchison

SKILLS

Leadership | Python | Verilog |

AREA OF EXPERTISE

Business: Management | Digital: RTL | Digital: Verification |

ADITYA ANAND

SKILLS

Cadence Encounter | Matlab | ngspice | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: FPGA Programming | System: Signal Integrity |

Jan Bělohoubek

SKILLS

C/C++ | Magic CAD | ngspice | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Digital: RTL | Digital: Synthesis | Digital: Verification |

Sergey Churayev

SKILLS

Cadence Encounter | Cadence Virtuoso | Electric CAD | Matlab | ngspice | Octave | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Circuits: Microcontrollers | Circuits: Sensors | Digital: RTL | Miscellaneous: Cryptography | System: FPGA Programming |

Raghu

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: DFT | Digital: RTL | Digital: Synthesis |

Elias Vieira

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Digital: Placement and Routing | Digital: RTL |

Anurag Darbari

SubIP and SoC Design Verification Engineer. Extends to running Full Chip Emulation on Palladium and Protium Platforms.

SKILLS

System Verilog | uvm | Verilog |

AREA OF EXPERTISE

Digital: RTL | SoC: Verification |

sampath vp

Semiconductor

SKILLS

Cadence Encounter | Leadership | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Bhagesh Choudhry Maheshwari

ASIC/FPGA Design Engineer | Former Intern in CERN | Former Cultural Ambassador of Pakistan in USA | Gold Medalist

SKILLS

Matlab |

AREA OF EXPERTISE

Digital: RTL |

Manish Mahajan

I am a design / verification Engineer for ASIC and FPGA .

SKILLS

C/C++ | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification |

Timothy Linden

SKILLS

C/C++ | Matlab | Software Developer | VHDL |

AREA OF EXPERTISE

Digital: RTL | System: FPGA Programming |

Thomas Parry

Mixed-signal designer

SKILLS

Cadence Virtuoso | Calibre | Matlab | Netgen | ngspice | Python | Spectre | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Digital: RTL | Digital: Verification |

Mustafa Khairallah

I am a Ph.D. student at the School of Physical and Mathematical Sciences, NTU, Singapore. I co-designed the Romulus and Remus families of lightweight authenticated encryption modes with Tetsu Iwata, Kazuhiko Minematsu and Thomas Peyrin, which are the basis of three candidates for the NIST Lightweight Cryptography Competition. Previously, I got my BSc. in Electronics Engineering from Alexandria University, Egypt. My main research focus is the practical aspects of Symmetric Key Cryptography, which includes: Physical Security, Hardware Implementations, Practical Cryptanalysis and Primitive Design. Previous research projects also included the acceleration of Fully Homomorphic Encryption and Design and Verification of Digital Circuits.

SKILLS

C/C++ | Cadence Encounter | Matlab | Octave | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL | perl |

AREA OF EXPERTISE

Academic: Research | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification |

Ken Pettit

Digital Systems and Software Engineer (formerly in management VP and Director of engineering).

SKILLS

C/C++ | Leadership | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB |

Sanjeev Sreeganesh Sasalu

SKILLS

AREA OF EXPERTISE

Loester Franco Botelho

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification | System: PCB |

Alexander Stanitzki

Analog/MS/RF IC designer

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Diva | Leadership | Python | SKILL | Spectre | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Business: Design Services | Circuits: Communication | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: Fabrication Process |

Matt Venn

Electronic engineer and science communicator.

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

Manar Abdelatty

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

Phillip Pearson

SKILLS

C/C++ | Python | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | System: FPGA Programming | System: PCB |

Vladimir Milovanović

SKILLS

Leadership |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Circuits: Communication | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL |

Harrison Pham

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

Gaurav Kumar K

PhD Student, School of Electrical and Computer Engineering, Purdue University, USA. Research interests include Mixed Signal Circuits, High Speed Circuits and Digital System Design

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Communication | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Russell Friesenhahn

Hardware developer with FPGA and previous small test ASIC experience.

SKILLS

C/C++ | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Elliot Buller

SKILLS

C/C++ | System Verilog |

AREA OF EXPERTISE

Digital: RTL |

Anton Blanchard

SKILLS

C/C++ | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Lakshana Ramalingam

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

Tore Leikanger

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Octave | Python | Software Developer | System Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Analog: Design | Analog: Layout | Digital: RTL | Digital: Synthesis | Digital: Verification | System: PCB |

Laurent Rougé

SKILLS

C/C++ | Python | VHDL | ASIC | FPGA | SoC |

AREA OF EXPERTISE

CAD: Scripting | CAD: Tool Development | Circuits: Communication | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Boobalan Deiveegan

SKILLS

System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | Digital: Verification |

M. Shalan

SKILLS

ASIC | C/C++ | EDA | Perl | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Teaching | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Pavan Sai

I am a final year B.Tech undergrad from India highly passionate about digital system design.

SKILLS

C/C++ | Leadership | Matlab | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | System: FPGA Programming |

Leonidas Kosmidis

I'm a Senior Researcher at the Barcelona Supercomputing Center and Junior Faculty at Polytechnic University of Catalonia (UPC). I'm the recipient of the RISC-V Educator of the Year Award 2019, for the advanced graduate course Processor Design I'm teaching at UPC, which is focused on the design of high-performance safety-critical systems. I'm the PI of the GPU4S project funded by the European Space Agency (ESA) in which we are investigating the applicability of embedded GPUs in space.

SKILLS

C/C++ | Electric CAD | Leadership | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Verification | SoC: Verification |

Dan Rodrigues

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

Klaus V

Analog mixed signal Asic design

SKILLS

AREA OF EXPERTISE

Sanggun Kim

SKILLS

C/C++ | python | System Verilog | Verilog |

AREA OF EXPERTISE

Business: Sales | Digital: RTL |

vasundhara sanivarapu

SKILLS

System Verilog | verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | Digital: Verification |

Bill Patterson

SKILLS

C/C++ | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | Digital: Synthesis |

Jeremie Crenne

SKILLS

C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | CAD: Scripting | CAD: Tool Development | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Joel Sanchez Moreno

My name is Joel Sanchez Moreno I graduated as a Computer engineer and I currently work as a full time RTL design engineer for a start up. In addition, I am doing a part-time master on High Performance Computing on the Universitat Politècnica de Catalunya (UPC)

SKILLS

Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: RTL |

Anthony Kung

Hi, I'm an Electrical & Computer Engineering + Computer Science student at Oregon State University.

SKILLS

C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | System: FPGA Programming |

Steven Herbst

I'm a PhD student working to make mixed-signal chip design more accessible, drawing inspiration from software development techniques. Prior to starting the PhD program, I spent a number of years working in industry at both the chip- and PCB-level on optical sensors and power systems.

SKILLS

C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | Spectre | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Verification | System: FPGA Programming | System: PCB |

Sylvain Munaut

SKILLS

C/C++ | Eagle CAD | Python | Scilab | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | System: FPGA Programming | System: PCB |

Zain Rizwan Khan

Research Associate at Micro Electronics Research Lab (MERL) working as a hardware design engineer.

SKILLS

C/C++ | System Verilog | UVM | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification |

Muhammed Ceylan Morgul

UVA HPLP

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Python | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Circuits: Memory | Circuits: Microcontrollers | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: Floorplanning | System: Test Equipment |

Daniel Limbrick

I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.