profiles search for area of expertise: Digital: Verification
103 results
Kranthi Kumar Pamarthi
I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.
SKILLS
MAYANK VASHISHT
Interested in Design, Verification, and Hand-off of Analog IPs. Worked on the definition, modeling, design, verification of DC-DC converters, Chargers, Ideal-Diodes, LDOs, Regulators, Bandgap references, Current limiting and sensing architectures. Excited for challenges in Analog Design, Layout and Post-silicon verification.
SKILLS
- Cadence Virtuoso | Matlab | Octave | SKILL | Spectre | System Verilog | Verilog |
Mauricio De Carvalho
SKILLS
- C/C++ | Cadence Encounter | Software Developer | System Verilog | Verilog | VHDL |
Jonathan Richard Robert Kimmitt
Research Associate at University of Cambridge
SKILLS
- Verilog |
AREA OF EXPERTISE
Venkata Nitheesh Kumar Reddy Kethu
AREA OF EXPERTISE
Preetham Lakshmikanthan
SKILLS
- C/C++ | System Verilog |
AREA OF EXPERTISE
Harika
SKILLS
- System Verilog | UVM |
AREA OF EXPERTISE
Peter Atkinson
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Ganesh V
ECE undergraduate looking to gain expertise in Analog/digital design.
SKILLS
- Cadence Virtuoso | Python | SKILL | Software Developer | Spectre | Verilog |
AREA OF EXPERTISE
Ronan BARZIC
Principal Engineer at ONiO AS
AREA OF EXPERTISE
Sushma kumari
-
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AREA OF EXPERTISE
Rohit Jindal
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AREA OF EXPERTISE
Vincent Trudel-Lapierre
AREA OF EXPERTISE
Ben Marshall
SKILLS
- C/C++ | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Vishal Prafulkumar Katigar
Trained in ASIC verification from Maven silicon Bengaluru
Also having experience in embedded domain (PCB layout design)
SKILLS
- C/C++ | Perl | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Ankit Agrawal
I am VLSI Design & Verification Engineer.
SKILLS
- Aldec RivieraPro | C/C++ | Digital Electronics | System Verilog | UVM | Verilog | Xilinx ISE |
AREA OF EXPERTISE
Semiu A. Olowogemo
AREA OF EXPERTISE
Sagar Jadhav
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AREA OF EXPERTISE
harikrishna
Physical Design Engineer
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
Mustafa Khan Patan
AREA OF EXPERTISE
Swapnil ..
Chief Engineer
Embedded Systems, VLSI startup
SKILLS
- C/C++ | Matlab | System Verilog |
AREA OF EXPERTISE
waibhav sonewane
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AREA OF EXPERTISE
Gordon Aplin
IC Design Engineer
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Magic CAD | ngspice | Perl | Tanner L-Edit | Verilog | VHDL |
AREA OF EXPERTISE
Sumanta
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | System-C | Verilog |
AREA OF EXPERTISE
J. Rodriguez
Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.
SKILLS
- C/C++ | System Verilog | System-C | VHDL |
AREA OF EXPERTISE
Pooja bilkar
SKILLS
- C/C++ | Cadence Virtuoso | Python | Verilog |
AREA OF EXPERTISE
Igor Danilov
SKILLS
- Cadence Encounter | Cadence Virtuoso | Python | Spectre | System Verilog | Tcl/Tk |
AREA OF EXPERTISE
Luc Wong
I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Lakshya Kailkhura
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AREA OF EXPERTISE
D S NAVEEN
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AREA OF EXPERTISE
pranay reddy
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Verilog |
AREA OF EXPERTISE
Anton Balbekov
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Leadership | Netgen | Python | SKILL | Software Developer | Spectre | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: Power Integrity |
Asier Goikoetxea
SKILLS
- C/C++ | System Verilog | Verilog |
AREA OF EXPERTISE
Dave Cameron
SKILLS
- C/C++ | Magic CAD | Python | Software Developer | System Verilog | Verilog |
AREA OF EXPERTISE
Laurent Lamesch
HW development engineer
AREA OF EXPERTISE
- Analog: Design | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Test Equipment |
eldho george
SKILLS
- Cadence Virtuoso | Matlab | Perl | System Verilog | Verilog |
AREA OF EXPERTISE
Yuan Mei
An experimental physicist through sensor and instrumentation development.
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Leadership | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |
ABDULLAH RAZA Khan
SKILLS
- C/C++ | Synthesis | Digital design |
AREA OF EXPERTISE
Bhaskar Moni
VLSI Engineer
SKILLS
- C/C++ | Cadence Virtuoso | Verilog |
AREA OF EXPERTISE
ALAIN POTTECK
VLSI design project manager
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AREA OF EXPERTISE
Yunzhe Li
MS IC Designer, focusing on imager design in deep submicron technologies
AREA OF EXPERTISE
Brian Glod
AREA OF EXPERTISE
- Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |
Mohammed Nabeel
Learner for life
SKILLS
- Perl | Python | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Federico Paredes
Digital designer experienced in high-speed ASICs for optical/copper transceivers, including DSPs, error correction and SoC support.
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Python | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
Nambi
AREA OF EXPERTISE
Muhammad Awais Bin Altaf
SKILLS
- Cadence Virtuoso | Calibre | Matlab | Spectre | Verilog |
Marco Merlin
Electronics Engineer with 10 years experience in microelectronics and research.
Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms.
Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to.
During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.
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AREA OF EXPERTISE
Caio Alonso da Costa
SKILLS
- C/C++ | Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
ardencaple
Semiconductor professional with 40 years experience.
I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.
AREA OF EXPERTISE
Paulo Roberto Bueno de Carvalho
Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes.
He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.
SKILLS
- C/C++ | Cadence Encounter | Python | System Verilog | Verilog | VHDL |
Hossam Hassan
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
- Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming | System: PCB |
Bob Ledzius
35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.
SKILLS
- C/C++ | Leadership | Matlab | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
- Business: Design Services | Business: Management | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: PCB |
Mahmoud Abdelgawad
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Mostafa Elbediwy
Teaching assistant for ASIC/FPGA and digital ICs courses.
SKILLS
- C/C++ | Cadence Virtuoso | Calibre | Matlab | System Verilog | Verilog |
AREA OF EXPERTISE
Jose Maria Hinojo
SKILLS
- Allegro | Altium | C/C++ | Cadence Assura | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Perl | Tcl/Tk | VHDL |
AREA OF EXPERTISE
Mahruz Aziz
SKILLS
- Verilog |
AREA OF EXPERTISE
Tigran Poghosyan
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Hercules | Python | Tcl/Tk |
AREA OF EXPERTISE
Rakesh Singanahalli
Hello I am Rakesh , I am pursuing my Under Graduation in Electronics and Communication Engineering at KLE Technological University, Hubballi. I am looking ahead work in Digital VLSI Domain. :D
SKILLS
- C/C++ | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Awnind Abhay Shrivastava
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AREA OF EXPERTISE
Tung Hoang
R&D Engineer
SKILLS
- Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Vivek Parmar
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | ngspice | Octave | Python | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |
Geethanand N
Ex intel professional with over 5 years of experience in front end Vlsi
SKILLS
- Perl | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Ippei Akita
An analog mixed-signal circuit designer for low-power precision sensor interfaces. See https://staff.aist.go.jp/ippei.akita/
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Python | Spectre | Verilog |
AREA OF EXPERTISE
- Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Communication | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: Chip Editing | System: PCB | System: Test Equipment |
Joseph Kiniry
Dad. Partner. Scientist. Activist. Maker. — He/His
SKILLS
- C/C++ | Cadence Virtuoso | Eagle CAD | Leadership | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | Bluespec | Chisel | EDA R&D |
AREA OF EXPERTISE
- Academic: Research | Business: Design Services | Business: Management | CAD: Tool Development | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: Quality Assurance | System: Test Programming | Miscellaneous: Formal Methods |
Stefano
SKILLS
- C/C++ | Matlab | System Verilog | Tcl/Tk |
AREA OF EXPERTISE
Rahul Behl
SKILLS
- Perl | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Kiran Prasad Kanaparthi
SKILLS
- C/C++ | Leadership | Perl | Python | System Verilog |
AREA OF EXPERTISE
Hanssel Morales
AREA OF EXPERTISE
Amit Bachiphale
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AREA OF EXPERTISE
Chaitanya CVS
SKILLS
- Perl | System Verilog | System-C | Verilog |
AREA OF EXPERTISE
Guy Hutchison
SKILLS
- Leadership | Python | Verilog |
AREA OF EXPERTISE
Mayuresh Rajwadkar
Silicon Entrepreneur with extensive experience in Digital Physical Design, EDA and HPC Infrastructures for Electronic Design.
SKILLS
- Cadence Encounter | Cadence Virtuoso | Calibre | Hercules | Leadership | Perl | Python | Spectre | Verilog |
AREA OF EXPERTISE
Jan Bělohoubek
AREA OF EXPERTISE
Manish Mahajan
I am a design / verification Engineer for ASIC and FPGA .
SKILLS
- C/C++ | System Verilog | Tcl/Tk | Verilog |
AREA OF EXPERTISE
Thomas Parry
Mixed-signal designer
SKILLS
- Cadence Virtuoso | Calibre | Matlab | Netgen | ngspice | Python | Spectre | Tanner L-Edit | Verilog | VHDL |
AREA OF EXPERTISE
Mustafa Khairallah
I am a Ph.D. student at the School of Physical and Mathematical Sciences, NTU, Singapore. I co-designed the Romulus and Remus families of lightweight authenticated encryption modes with Tetsu Iwata, Kazuhiko Minematsu and Thomas Peyrin, which are the basis of three candidates for the NIST Lightweight Cryptography Competition. Previously, I got my BSc. in Electronics Engineering from Alexandria University, Egypt. My main research focus is the practical aspects of Symmetric Key Cryptography, which includes: Physical Security, Hardware Implementations, Practical Cryptanalysis and Primitive Design. Previous research projects also included the acceleration of Fully Homomorphic Encryption and Design and Verification of Digital Circuits.
SKILLS
- C/C++ | Cadence Encounter | Matlab | Octave | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL | perl |
AREA OF EXPERTISE
Ken Pettit
Digital Systems and Software Engineer (formerly in management VP and Director of engineering).
SKILLS
- C/C++ | Leadership | Software Developer | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Soumil Krishnanand Heble
AREA OF EXPERTISE
Loester Franco Botelho
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- C/C++ | Cadence Virtuoso | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Abdullah YILDIZ
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AREA OF EXPERTISE
Bilal Zafar
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Leadership | Magic CAD | Matlab | ngspice | Perl | Python | System Verilog | Verilog |
AREA OF EXPERTISE
Jayesh parmar
ASIC verification engineer
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AREA OF EXPERTISE
Tore Leikanger
SKILLS
- C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Octave | Python | Software Developer | System Verilog |
AREA OF EXPERTISE
Osaze Shears
Osaze Shears is passionate about many engineering and computational concepts. These include embedded systems, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and microprocessor technologies. Osaze spends his free time tutoring other students who are interested in learning to become better computer scientists and engineers to benefit the greater society.
Osaze is currently a PhD student at Virginia Tech conducting research under the Multifunctional Integrated Circuits and Systems (MICS) lab. His research interests include:
• Spiking Neural Networks
• Hardware Acceleration
• SoC Design with ASICs and FPGAs
• Deep Learning
• Edge Computing
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AREA OF EXPERTISE
Theodoric Xie
ASIC design engineer at Google advancing high-level synthesis and next-generation computer architectures.
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AREA OF EXPERTISE
Boobalan Deiveegan
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AREA OF EXPERTISE
M. Shalan
AREA OF EXPERTISE
Pavan Sai
I am a final year B.Tech undergrad from India highly passionate about digital system design.
SKILLS
- C/C++ | Leadership | Matlab | Python | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Leonidas Kosmidis
I'm a Senior Researcher at the Barcelona Supercomputing Center and Junior Faculty at Polytechnic University of Catalonia (UPC). I'm the recipient of the RISC-V Educator of the Year Award 2019, for the advanced graduate course Processor Design I'm teaching at UPC, which is focused on the design of high-performance safety-critical systems. I'm the PI of the GPU4S project funded by the European Space Agency (ESA) in which we are investigating the applicability of embedded GPUs in space.
SKILLS
- C/C++ | Electric CAD | Leadership | Software Developer | Verilog |
AREA OF EXPERTISE
Matthew Ballance
SKILLS
- C/C++ | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog |
AREA OF EXPERTISE
vasundhara sanivarapu
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AREA OF EXPERTISE
Jeremie Crenne
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- C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |
AREA OF EXPERTISE
Surendra Kumar
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AREA OF EXPERTISE
Steven Herbst
I'm a PhD student working to make mixed-signal chip design more accessible, drawing inspiration from software development techniques. Prior to starting the PhD program, I spent a number of years working in industry at both the chip- and PCB-level on optical sensors and power systems.
SKILLS
- C/C++ | Cadence Virtuoso | Matlab | ngspice | Python | Spectre | System Verilog | Verilog |
AREA OF EXPERTISE
Zain Rizwan Khan
Research Associate at Micro Electronics Research Lab (MERL) working as a hardware design engineer.
SKILLS
- C/C++ | System Verilog | UVM | Verilog |
AREA OF EXPERTISE
Muhammed Ceylan Morgul
UVA HPLP
Daniel Limbrick
I am currently an Associate Professor in the Electrical and Computer Engineering Department at North Carolina Agricultural and Technical State University (NC A&T). As director of the Automated Design for Emerging Process Technologies (ADEPT) laboratory at NC A&T, I research the following questions: (1) how can we make computers more reliable in harsh environments (i.e., ionizing particles, malicious fault injection) and (2) how can we extend Moore’s law (e.g., 3D IC)? To answer these questions, he interrogates the traditional abstraction layers of integrated circuit design (i.e., functional description, circuit design, physical design) to discover design methodologies that are more relevant to these goals.
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AREA OF EXPERTISE
Sathyanarayanan
I am accomplished digital design engineer having 8 years of industrial expertise .
I am currently working on IP design and IP integrations stuffs .
SKILLS
- C/C++ | Cadence Virtuoso | System Verilog | Verilog |
AREA OF EXPERTISE
Ahmed Yiwere
SKILLS
- C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | ngspice | Perl | Python | System Verilog | Verilog | VHDL |
Arthur Fortini
AREA OF EXPERTISE
Klaus Strohmayer
Independent Digital Design and Verification Expert with more than 20+ years of experience and founder of semify. While working for established semiconductor companies like Infineon, Dialog Semiconductor and NXP I was responsible for bringing ideas into working ASICs. I developed USound’s first ASIC from FPGA based prototyping to tapeout with minimal resourcing, demanding timeline and tight area and power consumption constraints. Currently I'm acting as a consultant for easyIC and Cypress / Infineon. In addition I'm is also lecturer at the FH Joanneum Graz and guest lecturer at the Technical University Graz.
