profiles search for area_of_expertise: Soc

121 results

Mohamed Bamakhrama



Alberto Gomez

Passionate about Open Source RF Design!




Engineer, who typically worked in start up environment. So do A-Z, a-z and 1 - infinity if something has to work

Stepan Sutula

I received the B.S. degree in Industrial Electronics Engineering from the Universitat Politècnica de Catalunya, Spain, in 2007, and the M.S. degree in Micro- and Nanoelectronics Engineering in 2009 and the Ph.D. degree in Microelectronics and Electronic Systems in 2015 both from the Universitat Autònoma de Barcelona, Spain. From 2006 to 2008, I was with Investigation Total Ware, S.A., Spain, where I was engaged in analog and mixed-signal circuit design for highly reliable wireless telecommunication systems. From 2008 to 2015, I was with the Integrated Circuits and Systems design group at the Institut de Microelectrònica de Barcelona, CNM, CSIC, Spain, designing low-power high-precision mixed-signal ASICs for integrated smart sensors and IP blocks. From 2015 to 2016, I was with Broadcom Ltd., Barcelona, Spain, developing low-power CMOS IPs like low-temperature-drift oscillators, varible-temperature-coefficient current/voltage generators, temperature sensors, cross-domain level shifting and biasing circuits, touch-sensor transmitter drivers. I am co-author of 12 publications and participant in several research and industrial projects using a wide range of CMOS technology nodes. I am recipient of the 2007 Highest Grade Point Average in the Graduating Class Award, the 2014 Best Paper Award and the 2015 Student Best Paper Award Honorable Mention. My skills include: high-performance continuous-time/switched-capacitor circuits such as low-power high-resolution ADCs/DACs using Class-AB OpAmps; system high-level modeling (SciPy/Sage, Matlab); system electrical-level modeling (Verilog/-A/-AMS); EKV circuit-level modeling; full-custom IC design cycle (gEDA Tools/Cadence Virtuoso: from schematics to layout and verification); development of low-noise and low-distortion test equipment (including microcontrollers and FPGAs) and software (using C++, Tcl, VB, Python); and, experimental IC measures and parameter extraction.




I am working into Soc verification




iam presently working as an Soc verification Engineer



Nishant Pani



Deepak Siddharth Parthipan

I am Digital/SoC Design and Verification enthusiast.


bhavik balwani

i am working as physical design engineer






Pushkaraksha K M

Physical design engineer with strong expertise in CAD and low power methodologies

Mahmoud Youssuf Ahmad

Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.

Paulo Roberto Bueno de Carvalho

Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.

Bob Ledzius

35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.


Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.


IP & SoC Verification Engineer


fabien andrade

Graduated with a Micro-electronics Master from Bordeaux university, France, I have now 18 years of experience. Worked in France, England, Belgium and Brazil, within 5 companies. Implemented physical design flows, recruited, trained and supervised trainees to experienced engineers, I have a vast experience in setting up complete flow (2 companies were startups), as well as signing off important design within NXP and CSR, all to successful first time right silicons. Able to work in total independence as well as within a team, I consider myself as optimist, result focused, with attention to detail while keeping a good trade between time to market and risk taking.


Physical Design Engineer

Vishal Prafulkumar Katigar

Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)


Experienced Analog Design Engineer with strong background in HV CMOS ASICs.

Marco Merlin

Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.

Umer Imran

Umer Imran is eager to work in the field of Computer Architecture and Memory Consistency. He is currently working as a Design Verification Engineer at Lampro Mellon, a training firm with the vision to transform Pakistan’s talent pool into leaders of RISC-V based SoC design. He constantly aims to gain expertise in the various domains of SoC Design including IP Design, ASICs, and low power architectures.


Komal Javed

A young and ambitious individual, eager to apply my knowledge of Computer Architecture and VLSI Physical Design to develop hardware that is performance, power and area efficient, while actively contributing to the development and growth of the open-source semi-conductor industry

Ankit Agrawal

I am VLSI Design & Verification Engineer.


Interested in Design, Verification, and Hand-off of Analog IPs. Worked on the definition, modeling, design, verification of DC-DC converters, Chargers, Ideal-Diodes, LDOs, Regulators, Bandgap references, Current limiting and sensing architectures. Excited for challenges in Analog Design, Layout and Post-silicon verification.

Azhar Din

Passionate about engineering and electronics. Love teaching and mentoring. Highly experience in analogue and RF electronics and enjoy managing projects.

David Garner

An experienced mixed-signal IC design engineer / design manager with over 25 years experience. Has design and led the design of multiple mixed-signal ICs through to tapeout and silicon verification. Also experienced with the delivery of IP blocks. Worked across multiple market sectors.

Nishit Nathwani

I am a Master's student who has to know for learning and do experiments as well as for writing technical blogger. My website links are given below to connect with my open-source family of the VLSI champions.

Priyanka Dutta

current Phd Student in UCSC Hardware System Collective group formerly worked in Qualcomm Wireless R&D team as a design verification engineer

Klaus Strohmayer

Independent Digital Design and Verification Expert with more than 20+ years of experience and founder of semify. While working for established semiconductor companies like Infineon, Dialog Semiconductor and NXP I was responsible for bringing ideas into working ASICs. I developed USound’s first ASIC from FPGA based prototyping to tapeout with minimal resourcing, demanding timeline and tight area and power consumption constraints. Currently I'm acting as a consultant for easyIC and Cypress / Infineon. In addition I'm is also lecturer at the FH Joanneum Graz and guest lecturer at the Technical University Graz.

Bertrand PIGEARD

Hello, I'm an IC Designer Analog/RF with digital skills. I worked mainly on PLL for mobile tranceivers. I used to work on Cadence Design flow for 20 years.

vyas v





Mayuresh Rajwadkar

Silicon Entrepreneur with extensive experience in Digital Physical Design, EDA and HPC Infrastructures for Electronic Design.

Thiago Coura



Daniel J Wisehart

More than 25 years in FPGA design

Shivam Potdar

RISC-V Enthusiast GSoC 2020 @ FOSSi Foundation RA @ CAD Lab, IISc Bengaluru, India EE Senior @ NITK Mangalore, India

Geethanand N

Ex intel professional with over 5 years of experience in front end Vlsi

vinay k s

Verification engineer and quick learner and really enthusiastic to learn new things



Malcolm Smith

IC designer with more than 25 years post Ph.D. experience. Specialising in RF, RFIC, analog and mixed-signal. Wide experience in Architecture, system and circuit design. RF front-end module design for cellular with CMOS PA. Over 40 patents issued.

Pratika Tripathi

I am Pratika Tripathi. I am in my final year of Btech. I am very interested in physical designing of IC. I had even taken 3 courses of kunal ghosh sir on physical design, stay, and cts. I am doing my final year project in physical design.

Marc Rose

For most of my career, I was a CAD technology innovator and CAD system architect at Intel Corporation. I signed up recently for a Udemy class called "VSD - Making the Raven Chip: How to Design a RISC-V SoC." The class pointed me to Efabless.

Anurag Darbari

SubIP and SoC Design Verification Engineer. Extends to running Full Chip Emulation on Palladium and Protium Platforms.



Mustafa Khairallah

I am a Ph.D. student at the School of Physical and Mathematical Sciences, NTU, Singapore. I co-designed the Romulus and Remus families of lightweight authenticated encryption modes with Tetsu Iwata, Kazuhiko Minematsu and Thomas Peyrin, which are the basis of three candidates for the NIST Lightweight Cryptography Competition. Previously, I got my BSc. in Electronics Engineering from Alexandria University, Egypt. My main research focus is the practical aspects of Symmetric Key Cryptography, which includes: Physical Security, Hardware Implementations, Practical Cryptanalysis and Primitive Design. Previous research projects also included the acceleration of Fully Homomorphic Encryption and Design and Verification of Digital Circuits.

Micro Electronics Research LAB (MERL)

I am currently working as a Research Associate. We are doing research and development on RISC-V Technology.

Leonidas Kosmidis

I'm a Senior Researcher at the Barcelona Supercomputing Center and Junior Faculty at Polytechnic University of Catalonia (UPC). I'm the recipient of the RISC-V Educator of the Year Award 2019, for the advanced graduate course Processor Design I'm teaching at UPC, which is focused on the design of high-performance safety-critical systems. I'm the PI of the GPU4S project funded by the European Space Agency (ESA) in which we are investigating the applicability of embedded GPUs in space.




Osaze Shears

Osaze Shears is passionate about many engineering and computational concepts. These include embedded systems, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and microprocessor technologies. Osaze spends his free time tutoring other students who are interested in learning to become better computer scientists and engineers to benefit the greater society. Osaze is currently a PhD student at Virginia Tech conducting research under the Multifunctional Integrated Circuits and Systems (MICS) lab. His research interests include: • Spiking Neural Networks • Hardware Acceleration • SoC Design with ASICs and FPGAs • Deep Learning • Edge Computing

Theodoric Xie

ASIC design engineer at Google advancing high-level synthesis and next-generation computer architectures.

Gagan Gupta

I am an enthusiastic proponent of open source hardware. See my position paper on the topic:


Adroitec Systems is design Services Company for the VLSI and Embedded Software. Founded in 2017, Adroitec Systems is having Register Office at Visakhapatnam with branch offices in Bangalore. Adroitec Systems delivers cutting edge solutions across a diverse portfolio of services including Physical Design, Physical Verification, and Design Verification. With about 50 highly qualified employees.