VLSI circuit design engineer with significant experience in microprocessor design in semiconductor processes from 65nm to 10nm. Provided register file designs and design training for Intel Big Core and SOC projects. Helped create semi-automated array layout methodology. Established cross-organizational methodology for variation analysis in register files. Converged memory IP handling across multiple organizations.
Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design. Fiction writer (National Literature Award for Novel, 2011, Costa Rica)
Edward Joullian Endowed Chair in Engineering Oklahoma State University Department of Electrical and Computer Engineering VLSI Computer Architecture Research Group
Undergraduate in ECE & Economics at BITS Pilani, India. An enthusiast in IC Design, VLSI and Physical Design.
Experienced Senior Design Engineer with a demonstrated history of working in the electrical and electronic manufacturing industry. Skilled in DAC, SPICE, ADCs, Electronics Hardware Design, and Management. Strong engineering professional with a M-Tech focused in VLSI System Designs from Vallurupalli Nageswara Rao Vignana Jyothi Institute of Engineering &Technology and also a B-Tech Degree in the field of Electrical, Electronics and Communications Engineering from Mahatma Gandhi Institute of Technology.
Hello I am Rakesh , I am pursuing my Under Graduation in Electronics and Communication Engineering at KLE Technological University, Hubballi. I am looking ahead work in Digital VLSI Domain. :D