Tag results for: skills

Kranthi Kumar Pamarthi

I am passionate about all areas of VLSI Design and trying my level best to be an expert in the entire flow, analog, digital and mixed signal. Beyond chips, I like poetry, skating, skydiving, late night swimming and trekking in no particular order.

SKILLS

Magic CAD | Matlab | Netgen | ngspice | Octave | Python | System Verilog | Tcl/Tk | Verilog | VHDL | perl |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Circuits: Filters | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | System: FPGA Programming |

Armagan ERGUN

SKILLS

Cadence Encounter | Cadence Virtuoso | Eagle CAD | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Belal RAFFED

SKILLS

Analog CMOS CIrcuit | C/C++ | CIrcuit Design | Eagle CAD | Electric CAD | Matlab | ngspice | Object Oriented programming | PCB Design and Verification flow | Perl Scripting | Real Time Programming | RTL Simulation | Software Developer | System Verilog | Tanner L-Edit | Unix/Linux environments | Verilog | VHDL | VLSI/ASIC and SOC Development |

AREA OF EXPERTISE

Analg-ADC | Analog IC Design | Analog-ADC | Analog-Layout | Analog-Simulation | CAD: Scripting | Circuits-Microcontrollers | Digital-RTL | Digital-Verification | SOC-DV | System-Bring up | System-FPGA Emulation | System-PCB | System-Signal Integrity | System-Test Equipment |

Watson Huang

SKILLS

C/C++ | Python | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-RTL |

Juan Pablo Mena

SKILLS

C/C++ | Matlab | Python | Verilog |

AREA OF EXPERTISE

Digital-RTL |

Vishwajeet S B

I'm VLSI Design Engineer aspirant and like to work on design challenges in VLSI domain. I like to keep updated of cutting-edge technology in my field of interest.

SKILLS

Analog CMOS Circuit | Circuit Design | Matlab | Python | Verilog |

AREA OF EXPERTISE

Digital-RTL |

MAYANK VASHISHT

Interested in Design, Verification, and Hand-off of Analog IPs. Worked on the definition, modeling, design, verification of DC-DC converters, Chargers, Ideal-Diodes, LDOs, Regulators, Bandgap references, Current limiting and sensing architectures. Excited for challenges in Analog Design, Layout and Post-silicon verification.

SKILLS

Cadence Virtuoso | Matlab | Octave | SKILL | Spectre | System Verilog | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Filters | Circuits: Power Management | Circuits: Signal Processing | Digital: Verification | SoC: ESD | System: Test Programming |

Zaid Abukhalaf

SKILLS

C/C++ | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers |

Mauricio De Carvalho

SKILLS

C/C++ | Cadence Encounter | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Business: Design Services | Circuits: Microcontrollers | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming |

Aravind

I am a Application Engineer working for Cadence Design Systems and I facilitate the use of the Palladium Emulator at different Customers.

SKILLS

C/C++ | Perl | Python | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification | Design Automation |

Daniel J Wisehart

More than 25 years in FPGA design

SKILLS

C/C++ | Perl | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | SoC: Floorplanning | System: FPGA Programming |

Sai Srinivas TNS

SKILLS

Magic CAD | ngspice | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student |

Deepgandha Shete

M.Tech (VLSI Design and Embedded System) Actively looking for opportunities in the VLSI field

SKILLS

Cadence Virtuoso | DRC | LVS | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout |

Praneeth

SKILLS

Cadence Encounter | Cadence Virtuoso | Hercules | Perl | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Memory | Circuits: Power Management | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning |

dongxu yong

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Verilog |

AREA OF EXPERTISE

Analog: Design | Digital: RTL |

Saravanan Nanthakumar

I am a Master Degree holder in VLSI Design. I am interested in Analog Circuit Design.

SKILLS

C/C++ | Electric CAD | Magic CAD | Matlab | ngspice | Octave | Python | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching |

Chandana Archita Bachhu

SKILLS

Circuit Design | Perl | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-RTL |

Djamel DELLAA

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Eagle CAD | SPICE Opus | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Analog: Design | Analog: Layout | Analog: Verification | Digital: RTL | Digital: Synthesis |

shruthi karuturi

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Analog-Simulation |

John Sully

SKILLS

C/C++ | Software Developer | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Jonathan Richard Robert Kimmitt

Research Associate at University of Cambridge

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Venkata Nitheesh Kumar Reddy Kethu

SKILLS

C/C++ | Eagle CAD | Matlab | Octave | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Circuits: Filters | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Saul Rodriguez

I am Assistant Professor in Bio-Electronics. My research interests include analog mixed-signal ICs for medical applications, RFIC, and ultra-low power circuits.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Verification | Circuits: Communication | Circuits: Sensors |

Davy Huang

SKILLS

C/C++ | Circuit Design | Perl | Python | System-C | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | System-PCB | Digital-RTL |

Milan Kubavat

SKILLS

Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification |

Kullawat Chaowanawatee

SKILLS

C/C++ | Eagle CAD | Electric CAD | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Teaching | System: FPGA Programming | System: PCB |

Tim Edwards

Developer of open source EDA tools on Open Circuit Design

SKILLS

Analog CMOS Circuit | Analog IC Design | Analog/Digital Circuit Design | C/C++ | Circuit Design | Matlab | Python | Software Developer | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog | Analog IC | Analog IC Design | Analog-Layout | Analog-Mixed Signal-DV | Analog-Simulation | Analog-Verification | ASIC Design/Verification | Automatic Circuit Design | CAD-Dev | CAD-Scripts | Communication and Signal Processing | Cryptography | Design Automation | Digital-DFT | Evolutionary algorithm | signal processing | SOC-DV | SOC-ESD | SOC-Packaging | System-PCB | System-Signal-Integrity | Analog-ADC | Analog-LDO | Digital-BE | Digital-DV | Digital-RTL | System-DSP | System-Filters |

Samuel dos Santos Delgado

SKILLS

C/C++ | Magic CAD | Octave | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Circuits: Microcontrollers | Circuits: Signal Processing | System: FPGA Programming | System: PCB |

Salman Sheikh

Senior Design Engineer at NASA-Goddard., Greenbelt, MD

SKILLS

Eagle CAD | Python | Software Developer | Tcl/Tk | Verilog | VHDL | C |

AREA OF EXPERTISE

System: FPGA Programming |

Sebastien Riou

SKILLS

C/C++ | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | Miscellaneous: Cryptography |

Mohammed Essam Abd El Samee Soliman

I works as junior physical design engineer and I have passion in VLSI field specially in digital IC design. I have experience in writing RTL, test benches and in PnR flow.

SKILLS

Leadership | Matlab | Perl | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

CHINTADA.GAYATRI

Physical Design Engineer

SKILLS

C/C++ | Calibre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Verification | Business: Management | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Shubham Sarkar

SKILLS

Analog/Digital Circuit Design | C/C++ | Circuit Design | Python | Verilog |

AREA OF EXPERTISE

Digital-RTL |

Preetham Lakshmikanthan

SKILLS

C/C++ | System Verilog |

AREA OF EXPERTISE

Circuits: Power Management | Digital: Verification | SoC: Verification |

Eduardo Augusto da Costa

Eduardo is an Electrical Engineer engaged in hardware development with a true passion for developing and enhancing applications. While at university, he worked in a variety of projects, from VHDL in a SOC project, to a PCB for a power circuit, and even web interfaces for electronic devices network connected. He allies his technical background with great communication skills. He is used to and is passionate about working in diverse cultural environment as was his period as an international student in Japan. He also got a certification in in Digital Integrated Circuit Design and Project Flow with Cadence tools (IC Brazil Program). Currently he works at HT Micron, and is interested in positions related to chip design, hardware design, embedded software development and similar areas.

SKILLS

C/C++ | Cadence Encounter | Eagle CAD | Matlab | Octave | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Shriniket Sawant

Recent college graduate from San Jose State University with Masters in Electrical Engineering degree. Specialization - Digital Design and Verification.

SKILLS

Analog/Digital Circuit Design | Circuit Design | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-DV | Digital-RTL |

Hyogananda raj urs K

on my way to discover me

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Vachan U Bharadwaj

A recent graduate student from Syracuse University major in Electrical Engineering with focus in VLSI Designs

SKILLS

Cadence Encounter | Cadence Virtuoso | Eagle CAD | Perl | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: PCB | System: Signal Integrity |

Harika

SKILLS

System Verilog | UVM |

AREA OF EXPERTISE

Digital: Verification |

Rohit Yadav

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Electric CAD | Magic CAD | Matlab | Netgen | ngspice | Octave | Python | Scilab | SKILL | Spectre | SPICE Opus | System Verilog | System-C | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing |

Johanny Saenz

Electrical Engineer M.Sc. Microelectronics

SKILLS

Analog CMOS Circuit | Analog/Digital Circuit Design | Cadence Virtuoso | Matlab | Octave | Spectre | Verilog |

AREA OF EXPERTISE

Analog IC Design | Analog-ADC | Analog-Amplifiers | Analog-Mixed Signal-DV | Analog-Simulation | Analog: Design | Analog: Modeling | Analog: Simulation | CAD-Scripts | Cryptography |

Peter Atkinson

SKILLS

C/C++ | Cadence Encounter | Matlab | Octave | Perl | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Student | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Stephane Badel

Physical design engineer

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Eldo | Hercules | Matlab | ngspice | Octave | Perl | SKILL | Spectre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Layout | Analog: Simulation | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Rod

I'm an engineer with experience in analog IC design both in private companies as well as academia. Experienced in design of delay locked loop(DLL), clock recovery, field detectors, voltage limiters, operational amplifiers, current mirrors, bandgap reference and so on.

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Octave | Scilab | SKILL | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | CAD: Scripting | CAD: Tool Development | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Miscellaneous: Neural Networks | System: PCB |

Prashant Dabholkar

FPGA Design Engineer

SKILLS

Analog/Digital Circuit Design | Python | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-RTL |

Ganesh V

ECE undergraduate looking to gain expertise in Analog/digital design.

SKILLS

Cadence Virtuoso | Python | SKILL | Software Developer | Spectre | Verilog |

AREA OF EXPERTISE

CAD: Scripting | Digital: Verification |

Ronan BARZIC

Principal Engineer at ONiO AS

SKILLS

C/C++ | Magic CAD | ngspice | Python | System-C | Verilog |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Power Management | Digital: RTL | Digital: Verification | Miscellaneous: Neural Networks | SoC: Verification |

Luis Eduardo Rueda Guerrero

SKILLS

Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Scilab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Miscellaneous: Neural Networks |

Rohit Jindal

SKILLS

System Verilog |

AREA OF EXPERTISE

Digital: Verification |

Momen seliem

SKILLS

Calibre | Hercules | Magic CAD | Matlab | Perl | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing |

piyush gaur

i am currently persuing mtech from in vlsi design from DTU india.

SKILLS

Verilog | cmos integrated circuit |

AREA OF EXPERTISE

Digital: RTL |

Per Magnus Østhus

SKILLS

C/C++ | Perl | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis |

Stephen Wu

SKILLS

Cadence Virtuoso | Calibre | Diva | Eldo | Electric CAD | Magic CAD | Matlab | Netgen | ngspice | Octave | Spectre | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Sensors | Circuits: Signal Processing |

Stephan Ahles

SKILLS

C/C++ | Cadence Virtuoso | Eldo | Electric CAD | Leadership | Matlab | ngspice | Octave | Python | SKILL | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Business: Design Services | Business: Marketing | Business: Sales | CAD: Scripting | Circuits: Communication | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis |

Vincent Trudel-Lapierre

SKILLS

C/C++ | Matlab | Octave | Python | Scilab | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | Miscellaneous: Cryptography | Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Test Equipment |

Karim Abdel Hamid

SKILLS

C/C++ | Python | Software Developer | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Tim Whitfield

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

Ben Marshall

SKILLS

C/C++ | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Circuits: Microcontrollers | Digital: RTL | Digital: Verification | Miscellaneous: Cryptography |

Menaka Sajjan

SKILLS

Cadence Encounter | Cadence Virtuoso | Perl | Verilog | VHDL |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: ESD |

Shilpa Prabhu

VLSI Design Engineer

SKILLS

Cadence Encounter | Cadence Virtuoso | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Shubham Gajbhiye

SKILLS

Electric CAD | ngspice | Verilog |

AREA OF EXPERTISE

Academic: Student |

Christoph Maier

Mad Scientist

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eagle CAD | SKILL | Spectre | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Modeling | Analog: Simulation | Digital: Synthesis | Miscellaneous: Neural Networks |

Emre Goncu

SKILLS

Cadence Encounter | Cadence Virtuoso | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Fyyaz Khan

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Amit Prakash Gonnagar

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Electric CAD | Magic CAD | ngspice | Perl | Spectre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Circuits: Power Management | Digital: Placement and Routing | Digital: Synthesis | SoC: ESD | SoC: Floorplanning | System: Chip Editing | System: Fabrication Process | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Programming |

Vishal Prafulkumar Katigar

Trained in ASIC verification from Maven silicon Bengaluru Also having experience in embedded domain (PCB layout design)

SKILLS

C/C++ | Perl | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Microcontrollers | Circuits: Sensors | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: PCB |

Ankit Agrawal

I am VLSI Design & Verification Engineer.

SKILLS

Aldec RivieraPro | C/C++ | Digital Electronics | System Verilog | UVM | Verilog | Xilinx ISE |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | SoC: Verification |

Augustine Kuo

Vice President of Engineering - Seamless Microsystems. We design high performance AFEs using proprietary and patented technology that encodes the signal in the time-domain instead of voltage or current. This enables us to design low-power ADCs and amplifiers in scaled CMOS. Contact us if you'd like to hear more and engage our services.

SKILLS

Cadence Virtuoso | Calibre | Diva | Matlab | Perl | SKILL | Spectre | System Verilog | Verilog |

AREA OF EXPERTISE

Analog: Design |

Ira Chayut

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | SoC: Verification |

Pablo Cayuela

SKILLS

C/C++ | Electric CAD | Matlab | Octave | Scilab | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Digital: RTL | System: FPGA Programming |

Santhosh

IP & SoC Verification Engineer

SKILLS

Perl | System Verilog | Verilog | VHDL | UVM |

AREA OF EXPERTISE

Digital: Verification | SoC: Verification |

MD AKRAMUDDIN

SKILLS

C/C++ | Matlab | Perl | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-RTL |

Ömer Faruk Irmak

SKILLS

C/C++ | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Student |

khaled

SKILLS

C/C++ | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

System: FPGA Programming |

Syed Arsalan Jawed

I have been working on Analog/Mixed-Signal Integrated Circuits design since last 16 years. I graduated from NED UET, Karachi in 2001 and then worked with Avaz Networks, a Silicon-Valley Company on RTL design and verification of a high-density Line Echo Cancellation Engine for a couple of years. Joined Linkoping University, Sweden in 2003 for Masters in SOC, which concluded with a Masters Thesis on Sigma-Delta Modulators with Fraunhofer Institute of Integrated Circuits, Germany in 2005. The same year I joined University of Trento and Fondazione Bruno Kessler, Trento, Italy for my PhD on Readout Interface Design for MEMS Capacitive Microphones. Worked with ST-Microelectronics, Milano and Analog-Devices, Copenhagen as a Guest PhD Student. This Phd results in 20+ publications and 2 patents with 3 successful MEMS Readout ASICs.

SKILLS

Analog | Analog CMOS Circuit | Analog IC Design | Analog/Digital Circuit Design | C/C++ | Circuit Design | Matlab | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog | Analog IC | Analog IC Design | Analog-ADC | Analog-Amplifiers | Analog-Layout | Analog-Modeling | Analog-Simulation | Analog-Verification | ASIC Design/Verification | Digital-RTL |

Nanditha Rao

SKILLS

Cadence Encounter | Leadership | Magic CAD | ngspice | Verilog |

AREA OF EXPERTISE

Academic: Teaching | Digital: RTL | System: FPGA Programming | System: Signal Integrity |

Aurelien

SKILLS

Verilog | C |

AREA OF EXPERTISE

System: FPGA Programming |

Saroj Rout

Provides mixed-signal CMOS training to academia using open-source tools and also solution for the consumer and automotive industry.

SKILLS

Calibre | Eagle CAD | Magic CAD | Matlab | ngspice | Octave | Perl | Python | Scilab | SKILL | Spectre | System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | CAD: Scripting | Circuits: Filters | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | SoC: ESD | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Semiu A. Olowogemo

SKILLS

C/C++ | Cadence Virtuoso | Perl | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Sagar Jadhav

SKILLS

System Verilog | Verilog |

AREA OF EXPERTISE

Digital: Verification | SoC: Verification |

Mohamed Salem Abdelgalil

SKILLS

Perl | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | System: FPGA Programming |

yalcin balcioglu

SKILLS

System Verilog |

AREA OF EXPERTISE

Digital: RTL |

Francesco Renzini

SKILLS

Cadence Virtuoso | Eagle CAD | Eldo | Matlab | Spectre | System Verilog |

AREA OF EXPERTISE

Academic: Research |

ASHWINI C

I am Ashwini ,done Masters in Electronics. Very much interested to learn VLSI Physical Design

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

DIGITAL ELECTRONICS |

Rejoy Roy Mathews

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Student | Academic: Teaching | Digital: RTL |

Manoj S

Tech Lead

SKILLS

C/C++ | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | System: FPGA Programming |

harikrishna

Physical Design Engineer

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Mustafa Khan Patan

SKILLS

Tcl/Tk | Verilog |

AREA OF EXPERTISE

Digital: Verification |

Rifat Demircioglu

Managing Partner

SKILLS

C/C++ | Leadership | Matlab | Perl | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Business: Design Services | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming |

Edo Dwi Christianto

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Ankit Adesara

SKILLS

Cadence Virtuoso | Eldo | Magic CAD | Matlab | Perl | Scilab | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Memory | System: FPGA Programming |

Amudhan Balasubramanian

Over 25+ years of experience Silicon Engineer with focus on taking a Silicon from GDS2 to PRQ. Involved in Wafersort testing, Packaging, Packaging Testing, Silicon Characterisation - Electrical & Functional, Package Qualification, Reliablity testing and Yield management

SKILLS

Leadership | Python | Verilog |

AREA OF EXPERTISE

Business: Foundry Services | Business: Management | Business: Packaging | Business: PCB Manufacture | System: Fabrication Process | System: Packaging | System: PCB | System: Quality Assurance | System: Test Equipment | System: Test Programming |

Swapnil ..

Chief Engineer Embedded Systems, VLSI startup

SKILLS

C/C++ | Matlab | System Verilog |

AREA OF EXPERTISE

Business: Design Services | Digital: Verification |

waibhav sonewane

SKILLS

System Verilog |

AREA OF EXPERTISE

Digital: Verification |

SASWAT PADHY

SKILLS

Cadence Virtuoso | ngspice | Verilog |

AREA OF EXPERTISE

Academic: Student |

Nahush

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout |

Sun

Engineer, who typically worked in start up environment. So do A-Z, a-z and 1 - infinity if something has to work

SKILLS

C/C++ | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Communication and Signal Processing | signal processing | SOC-DV | Digital-DV | Digital-RTL |

Keith Raymond Fernandes

SKILLS

Cadence Encounter | Cadence Virtuoso | Matlab | Spectre | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Teaching |

Syed Asad Alam

Post-doctoral research fellow in the discipline of Software and Systems, School of Computer Science and Statistics, Trinity College Dublin, with a keen interest in learning new things, specially related to computer science and engineering. Around 4 years experience of teaching and research and more than 10 years of experience in architecture design, optimization, analysis, implementation and verification of digital and digital signal processing systems on FPGAs and ASICs. Diversifying research career by working on quantization of deep convolution neural networks. Author of three peer reviewed journal publications and five international conference publications.

SKILLS

C/C++ | Matlab | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | System: FPGA Programming |

Kevin Huynh

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Perl | Python | Scilab | Spectre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Circuits: Communication | Circuits: Filters |

Baker Mohammad

Experienced leader of industry and academia focusing on developing customized hardware accelerators for low power mobile, AI and IoT devices. Over 20-years hands-on experience in all aspects of SOC and processor design. Specialties: memory design (SRAM, regfile, CAM), VLSI design for best Power, Performance, and Area (PPA) design point. Power management and power conversion including dc/dc and ac/dc. Computer Architecture and Hardware accelerator using In-Memory-Computing and Emerging Technologies (RRAM)

SKILLS

Cadence Virtuoso | Leadership | Verilog |

AREA OF EXPERTISE

Academic: Teaching | Analog: Design | Circuits: Memory | Circuits: Power Management | Circuits: Signal Processing |

Alcides Silveira Costa

SKILLS

C/C++ | Leadership | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | CAD: Scripting | CAD: Tool Development | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Shyam K

SKILLS

Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Gordon Aplin

IC Design Engineer

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Magic CAD | ngspice | Perl | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

Swapnil Rawat

I am a student pursuing my masters in the field of VLSI

SKILLS

C/C++ | Cadence Virtuoso | System Verilog |

AREA OF EXPERTISE

Academic: Student |

Sumanta

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | Digital: Verification | System: FPGA Programming |

J. Rodriguez

Mixed background in computer science, applied mathematics and electrical engineering. Expert in algorithms to custom core development, system architecture, integration and functional verification.

SKILLS

C/C++ | System Verilog | System-C | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming |

OPNESH DEWANGAN

PURSUING M-TECH IN VLSI SPECIALIZATION , FROM IIIT BANGALORE

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

RAJA KUMAR MEHTA

Physical Design Engineer

SKILLS

C/C++ | Calibre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Verification | Business: Management | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Judd Jenne

SKILLS

C/C++ | Calibre | Python | Software Developer | System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | System: FPGA Programming |

Bertrand PIGEARD

Hello, I'm an IC Designer Analog/RF with digital skills. I worked mainly on PLL for mobile tranceivers. I used to work on Cadence Design flow for 20 years.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Diva | Matlab | ngspice | Octave | Perl | Python | Scilab | SKILL | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Communication | Circuits: Memory | SoC: Floorplanning |

harshitha yadavalli

SKILLS

Cadence Virtuoso | System-C | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Simulation | Digital: RTL | SoC: ESD |

sai palisetti

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Kris

SKILLS

Verilog |

AREA OF EXPERTISE

Academic: Student |

Krishna Ruparelia

SKILLS

Cadence Virtuoso | ngspice | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

trsohmers

SKILLS

Verilog |

AREA OF EXPERTISE

Miscellaneous: Neural Networks |

Dave Cox

Hardware Design Enthusiast

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Digital-RTL |

Braedon Salz

SKILLS

Analog/Digital Circuit Design | Software Developer | Verilog |

AREA OF EXPERTISE

System-Signal-Integrity | Analog-LDO | Digital-RTL |

Mustafa Tosun

I am a digital design/verification engineer. I have 2 years of full-time industry experience. In total, I have 4.5 years of experience in RTL design, Electronic Design Automation and Verification using VHDL/Verilog, Perl, Tcl and Linux. I was the #1 graduate of Bahcesehir University in Mechatronics Engineering in 2013

SKILLS

C/C++ | Matlab | Perl | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Communication and Signal Processing | Design Automation | Digital-RTL |

Will Burke

Hardware Engineer

SKILLS

Circuit Design | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Automatic Circuit Design | Digital-BE | Digital-RTL |

Chaitanya Parashar

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: RTL | SoC: Verification |

Ganesh Prasad B K

I am an electronics engineer currently working as an intern in STMicroelectronics.

SKILLS

Cadence Virtuoso | Calibre | Eldo | Matlab | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Simulation |

Mohammed Zakir Hussain

SKILLS

Cadence Encounter | Cadence Virtuoso | Magic CAD | Netgen | ngspice | Spectre | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Teaching | Digital: RTL | Digital: Synthesis |

MUVVA LAKSHMANKUMAR

SKILLS

C/C++ | Cadence Encounter | Perl | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning |

Jakk srinath

SKILLS

Analog/Digital Circuit Design | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-DV |

Meghana TJ

SKILLS

Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-RTL |

Muthukumar

SKILLS

Cadence Virtuoso | Calibre | Eldo | Python | Spectre | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Digital: Placement and Routing | Digital: Synthesis | System: FPGA Programming |

Ashutosh Jain

SKILLS

Analog/Digital Circuit Design | Matlab | Python | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-RTL |

Shahbaz Abbasi

Design engineer with combined R&D and industrial experience in developing analog/mixed signal ICs for applications including inductive position sensors and imager readouts. Proven abilities with widely used blocks including (but not limited to) filter, amplifier, ADC, DAC, voltage regulators, bandgap reference, ring/LC oscillator, comparator and custom digital logic circuitry. Experience with full tape-out flow including schematic design, analog/mixed-signal simulations, floor planning, layout, system-level verification and chip measurements. Strong familiarity with industry standard tools and instruments used for design, verification and testing such as Cadence, Synopsys, Mentor Graphics, and Keysight. Frontend digital hardware design (ASIC/FPGA) experience using Verilog HDL. Considerable exposure to ASIC backend flow (synthesis and PnR) using Synopsys Design Compiler and Cadence Innovus. Skilled with programming platforms such as MATLAB, C++, C#, Perl, UNIX Shell and VB. Strong education with Ph.D. and MSc. degrees in Electronics Engineering along with several peer-reviewed articles in IEEE journals.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | ngspice | Octave | Perl | Python | Scilab | Software Developer | Spectre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Filters | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB | System: Test Equipment | System: Test Programming |

Zheng Lai

SKILLS

C/C++ | Cadence Virtuoso | Python | Software Developer | Spectre | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Simulation | Analog: Verification | CAD: Tool Development | Circuits: Communication | Miscellaneous: Neural Networks | System: FPGA Programming |

Dejan Mirkovic

Electronics Engineer and Researcher with a demonstrated history of working in the higher education industry. Skilled in CAD/EDA tools for ASIC, PCB and FPGA design, scripting and programming. Education professional with a PhD in Electrical Engineering and Computer Science from University of Nis, Faculty of Electronic Engineering Nis, Serbia.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Matlab | Octave | Python | SKILL | Spectre | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | CAD: Scripting | Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming | System: PCB |

Pooja bilkar

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Synthesis | Digital: Verification |

ABHIJEET SINGH JADON

currently doing mtech in vlsi domain,want to gain knowledge in physical design and asic design flow

SKILLS

System Verilog |

AREA OF EXPERTISE

Academic: Student |

Darshan Guled

hello, my name is Darshan Guled, i am an engineering student and i am working on PICO RISc processor and RAVEN chip,

SKILLS

C/C++ | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Guy Hutchison

ASIC Designer and entrepreneur

SKILLS

C/C++ | Leadership | Python | Verilog | chisel |

AREA OF EXPERTISE

Digital: RTL | Miscellaneous: Cryptography |

Amogh Avinash

SKILLS

C/C++ | Computer Architecture | System Verilog | UVM | Verilog |

AREA OF EXPERTISE

Academic: Student |

Mario Vigliar

Mad about OSS system design, specialized in video compression and image processing, CNN and dedicated HPC architectures. New deals in low power design

SKILLS

C/C++ | Circuit Design | Matlab | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-RTL | System-DSP | System-Filters |

venkata sahith pulluru

SKILLS

Verilog |

AREA OF EXPERTISE

ASIC Design/Verification |

Ahmed Ramzy

SKILLS

C/C++ | Octave | System Verilog | Tanner L-Edit | Verilog | VHDL | ICC | DC |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Sajal Goyal

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | SoC: Verification |

Aditya Mudgal

Doing Mtech in VLSI Design from IIIT Bangalore

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Igor Danilov

SKILLS

Cadence Encounter | Cadence Virtuoso | Python | Spectre | System Verilog | Tcl/Tk |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | CAD: Scripting | Digital: RTL | Digital: Synthesis | Digital: Verification |

MADAN S

Analog circuit designer with passion in taking challenges .Interest in ADC,DAC,PLL,SDADC,LDO.Done layout of all these blocks.

SKILLS

Cadence Virtuoso | Calibre | Matlab | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Simulation |

MADHUSHREE

SKILLS

Analog CMOS Circuit | Analog/Digital Circuit Design | C/C++ | Perl | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | SOC-DV | Digital-DV | Digital-RTL |

Luc Wong

I've been worked as an Electrical Engineer for more than 20 years. I'd like to bring Artificial Intelligence to the EE design so that it can be "Self-driving".

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Perl | Python | Software Developer | Spectre | SPICE Opus | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services | Circuits: Communication | Circuits: Filters | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Neural Networks | SoC: ESD | SoC: Floorplanning | SoC: Verification | System: Chip Editing | System: FPGA Programming | System: PCB | System: Power Integrity | System: Signal Integrity | System: Test Equipment | System: Test Programming |

raju sake

SKILLS

Python | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research |

D S NAVEEN

SKILLS

System Verilog | Verilog |

AREA OF EXPERTISE

Digital: Verification |

Kaushik Parthasarathy

Electronics Engineer

SKILLS

Cadence Virtuoso | Electric CAD | Python | System Verilog |

AREA OF EXPERTISE

Analog: Design |

Baris Volkan Yildirim

Design engineer

SKILLS

Analog CMOS Circuit | Analog IC Design | Eldo | Matlab | Python | System Verilog |

AREA OF EXPERTISE

Academic: Research | Analog-Amplifiers | Analog: Design | Analog: Modeling | Analog: Verification | Business: Sales | Circuits: Filters | Circuits: Power Management |

Vincent Pinon

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Octave | Perl | Python | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | Circuits: Communication | Circuits: Power Management | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | System: Test Programming |

Sreekar

SKILLS

Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Prasanna Kumar Talari

just a beginner in asic

SKILLS

C/C++ | Matlab | Octave | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

Vitali

SKILLS

Cadence Virtuoso | Calibre | Diva | SKILL | Spectre | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Design Services |

Shuvadeep Kumar

SKILLS

Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Circuits: Memory | Digital: RTL |

SAKTHIVEL SM

VLSI PROFESSIONAL

SKILLS

C/C++ | Circuit Design | Matlab | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Cryptography | Digital-DFT | SOC-DV |

SANJAIKUMAR K

SKILLS

Analog/Digital Circuit Design | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-DV | Digital-RTL |

Disha Gulur

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Student |

Alok Parmar

SKILLS

ASIC | FPGA | SOC | Verilog |

AREA OF EXPERTISE

VLSI |

pranay reddy

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification |

Vrajesh Mistry

SKILLS

Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

System: FPGA Programming |

Shivani Shah

SKILLS

C/C++ | Matlab | Python | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

jatindersingh

SKILLS

Analog/Digital Circuit Design | C/C++ | Electric CAD | Magic CAD | ngspice | Python | System Verilog | System-C | Tcl/Tk | Verilog | VHDL | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog-SMPS | Analog: Simulation | Analog: Verification | Circuits: Memory | Circuits: Microcontrollers | Circuits: Power Management | Circuits: Sensors | Circuits: Signal Processing | Digital-DV | Digital-RTL | Digital: DFT | Digital: Placement and Routing | Miscellaneous: Neural Networks | SOC-DV | SoC: ESD | SoC: Floorplanning | SoC: Verification | System-DSP | System: Chip Editing | System: FPGA Programming |

Anton Babushkin

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

Alok kumar Pathak

SKILLS

Cadence Virtuoso | Magic CAD | ngspice | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design |

Hemant Juneja

SKILLS

C/C++ | Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout |

Srimanth

SKILLS

Eagle CAD | Python | Software Developer | Verilog |

AREA OF EXPERTISE

SoC: Verification |

Pavan Kumar Pothula

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Sandipan Sinha

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Digital: Placement and Routing | Digital: Synthesis | SoC: Floorplanning | System: Signal Integrity |

Akshay Godse

SKILLS

Cadence Virtuoso | Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Student |

James Tandon

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eagle CAD | Eldo | Leadership | Magic CAD | Matlab | Octave | Perl | Python | Scilab | Software Developer | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Business: Design Services | CAD: Tool Development | Circuits: Microcontrollers | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: Chip Editing | System: FPGA Programming | System: PCB |

Anton Balbekov

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Leadership | Netgen | Python | SKILL | Software Developer | Spectre | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Memory | Digital: Placement and Routing | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: Power Integrity |

Asier Goikoetxea

SKILLS

C/C++ | System Verilog | Verilog |

AREA OF EXPERTISE

Business: Design Services | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography |

Ankita Tiwari

Research Scholar

SKILLS

C/C++ | Leadership | ngspice | Python | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Circuits: Memory | Miscellaneous: Neural Networks | System: FPGA Programming |

KADAR A A

I am researcher with goals of developing high end technologies for the future.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Eldo | Leadership | Matlab | ngspice | Tanner L-Edit | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Digital: RTL | System: FPGA Programming |

Rupesh

I am working into Soc verification

SKILLS

Verilog |

AREA OF EXPERTISE

SOC-DV |

Sivaram P. Rao

SKILLS

Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-RTL |

Hardik Manocha

Intern with Synopsys VIP Group, Working on HDMI VIP Development

SKILLS

Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-DV | Digital-RTL |

Emre Kırkaya

PhD candidate on digital electronics

SKILLS

C/C++ | Matlab | Verilog |

AREA OF EXPERTISE

Digital-RTL |

Janak

SKILLS

Perl | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | SOC-DV | Digital-DV |

Edab

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Perl | Python | Software Developer | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | CAD: Scripting | Circuits: Communication | Circuits: Memory | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Miscellaneous: Neural Networks | System: FPGA Programming |

Dave Cameron

SKILLS

C/C++ | Magic CAD | Python | Software Developer | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | System: PCB |

Nikhil Prabhat Bhattiprolu

I just was learning to design the IPs.

SKILLS

Verilog |

AREA OF EXPERTISE

ASIC Design/Verification |

Deepak Siddharth Parthipan

I am Digital/SoC Design and Verification enthusiast.

SKILLS

C/C++ | Noob | Perl | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-DFT | SOC-DV | Digital-DV | Digital-RTL |

Mohamed Hassaneen Abd-elghafar Hassaneen Amer

I am an IC designer graduated from faculty of engineering at Ain-shams university in EGYPT in 2018, Now I am a reserch assistant at the IC laboratory of Ain-shams university. My graduation project was to design a decision feedback equalizer (DFE) of a high speed serial link transceiver form scratch to post layout simulations and system integration.

SKILLS

C/C++ | Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout |

Jean Carlos Schenuemann

SKILLS

C/C++ | Circuit Design | Matlab | Python | Software Developer | Verilog |

AREA OF EXPERTISE

signal processing | System-DSP | System-Filters |

BZERROUK

SKILLS

Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-DV | Digital-RTL |

CHIRAG KASLIWAL

Specialized Engineer in VLSI Design

SKILLS

Analog/Digital Circuit Design | C/C++ | Scilab | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-RTL |

Chaitanya Ummadisetty

SKILLS

Circuit Design | Perl | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

CAD-Dev | Design Automation | Digital-BE |

Vicente Amorim

SKILLS

C/C++ | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Teaching |

Shri Prakash

SKILLS

Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

SOC-DV | Digital-RTL |

JON MUNOA

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis |

Youssef Ahmed Mohammed

senior student-ECE departmant-faculty of engineering-ASU.

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Analog: Design |

Jose Joaquin Mendoza

SKILLS

C/C++ | Matlab | Python | Verilog |

AREA OF EXPERTISE

Communication and Signal Processing |

Hyunjin Noh

SKILLS

C/C++ | Matlab | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Design Automation | Digital-RTL |

Marcus N

System and database administrator, embedded systems hobbyist.

SKILLS

C/C++ | Perl | Python | Verilog |

AREA OF EXPERTISE

Circuits: Microcontrollers | Digital: RTL | System: FPGA Programming |

Vadim Platonov

Analog/Mixed-Signal IC Design Engineer

SKILLS

Analog CMOS Circuit | Analog | Analog IC Design | Analog/Digital Circuit Design | Circuit Design | Matlab | Verilog |

AREA OF EXPERTISE

Analog IC Design | Analog-Layout | Analog-ADC |

eldho george

SKILLS

Cadence Virtuoso | Matlab | Perl | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification | SoC: Verification |

Yuan Mei

An experimental physicist through sensor and instrumentation development.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Leadership | Matlab | ngspice | Python | SKILL | Software Developer | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification | CAD: Scripting | CAD: Tool Development | Circuits: Sensors | Circuits: Signal Processing | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment | System: Test Programming |

Joaquín Venegas

SKILLS

Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-RTL |

Ashbir Aviat Fadila

Analog and Mixed Signals Engineering Students

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Student |

Ronobir Das

BSEE graduating senior with a focus in digital design. I have taken coursework in Analog, Digital, Mixed Signal and RF IC design, and have experience using Cadence's tool suite as well as NI's AWR. I have also done multiple EDA centric courses in validation, formal and functional verification and Digital IC Testing

SKILLS

Analog/Digital Circuit Design | C/C++ | Python | System-C | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification |

Aleksandar Kostovic

Freelancer

SKILLS

Circuit Design | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog IC Design | ASIC Design/Verification | Automatic Circuit Design | System-PCB |

George Duffy

SKILLS

System Verilog |

AREA OF EXPERTISE

Digital: RTL |

Andre5

I am Electronic Engineer from Chile, I like DSP and radioastronomy applications an ordinary guy

SKILLS

C/C++ | System Verilog | Verilog | Design Compiler | Descartes | Formality | ICC | ICC2 | DFT | Xilinx ISE design suite | FPGA full flow | programming |

AREA OF EXPERTISE

Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | System: FPGA Programming | System: Quality Assurance | System: Test Programming |

Xianliang Chen

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Bhaskar Moni

VLSI Engineer

SKILLS

C/C++ | Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Digital: RTL | Digital: Verification |

ALAIN POTTECK

VLSI design project manager

SKILLS

Cadence Encounter | Cadence Virtuoso | Spectre | Verilog |

AREA OF EXPERTISE

Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Omar Abu El-ela

Electronics and Communication student

SKILLS

C/C++ | Eagle CAD | Matlab | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design |

Marco Adel

SKILLS

Cadence Virtuoso | Calibre | Leadership | Matlab | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design | Analog: Layout |

Mathieu Coustans

SKILLS

Cadence Encounter | Cadence Virtuoso | Eldo | Matlab | Spectre | System Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design |

Bo Lu

SKILLS

Matlab | System Verilog |

AREA OF EXPERTISE

Analog: Design |

Julio

RTL Engineer

SKILLS

C/C++ | Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Michael Vacek

SKILLS

C/C++ | Circuit Design | Matlab | Python | Software Developer | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Communication and Signal Processing | signal processing | System-PCB | Digital-RTL | System-DSP |

Eric Hawkins

Manager of Universal Avionics System Corporation(UASC) PLD design group. This group is tasked with designing, implementing and approving, in accordance with RTCA/DO-254 guidance, all ASIC/FPGA used in the Universal Avionics product line.

SKILLS

Analog/Digital Circuit Design | Circuit Design | Perl | Python | Scilab | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification |

Anton Paquin

EE student. ++ Neuromorphic circuits

SKILLS

Analog/Digital Circuit Design | Python | Verilog |

AREA OF EXPERTISE

CAD-Scripts | Digital-RTL |

Mohamed Abdelmotaal

Analog IC Designer

SKILLS

Analog CMOS Circuit | Analog | Analog IC Design | Circuit Design | Verilog |

AREA OF EXPERTISE

Analog IC Design | Analog-Amplifiers | Analog-Layout |

Mikhail

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: RTL |

Fabien Marteau

FPGA expert, interested by opensource tools for FPGA and for ASIC

SKILLS

Python | Verilog | VHDL |

AREA OF EXPERTISE

Business: Design Services |

Stepan Sutula

I received the B.S. degree in Industrial Electronics Engineering from the Universitat Politècnica de Catalunya, Spain, in 2007, and the M.S. degree in Micro- and Nanoelectronics Engineering in 2009 and the Ph.D. degree in Microelectronics and Electronic Systems in 2015 both from the Universitat Autònoma de Barcelona, Spain. From 2006 to 2008, I was with Investigation Total Ware, S.A., Spain, where I was engaged in analog and mixed-signal circuit design for highly reliable wireless telecommunication systems. From 2008 to 2015, I was with the Integrated Circuits and Systems design group at the Institut de Microelectrònica de Barcelona, CNM, CSIC, Spain, designing low-power high-precision mixed-signal ASICs for integrated smart sensors and IP blocks. From 2015 to 2016, I was with Broadcom Ltd., Barcelona, Spain, developing low-power CMOS IPs like low-temperature-drift oscillators, varible-temperature-coefficient current/voltage generators, temperature sensors, cross-domain level shifting and biasing circuits, touch-sensor transmitter drivers. I am co-author of 12 publications and participant in several research and industrial projects using a wide range of CMOS technology nodes. I am recipient of the 2007 Highest Grade Point Average in the Graduating Class Award, the 2014 Best Paper Award and the 2015 Student Best Paper Award Honorable Mention. My skills include: high-performance continuous-time/switched-capacitor circuits such as low-power high-resolution ADCs/DACs using Class-AB OpAmps; system high-level modeling (SciPy/Sage, Matlab); system electrical-level modeling (Verilog/-A/-AMS); EKV circuit-level modeling; full-custom IC design cycle (gEDA Tools/Cadence Virtuoso: from schematics to layout and verification); development of low-noise and low-distortion test equipment (including microcontrollers and FPGAs) and software (using C++, Tcl, VB, Python); and, experimental IC measures and parameter extraction.

SKILLS

Analog CMOS Circuit | Analog | Analog IC Design | Analog/Digital Circuit Design | C/C++ | Circuit Design | Matlab | Python | Software Developer | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog | Analog IC | Analog IC Design | Analog-Amplifiers | Analog-Layout | Analog-Mixed Signal-DV | Analog-Modeling | Analog-Simulation | Analog-Verification | ASIC Design/Verification | Automatic Circuit Design | CAD-Dev | CAD-Scripts | Communication and Signal Processing | Design Automation | Industrial Engineering | signal processing | SOC-DV | SOC-Packaging | System-PCB | System-Power-Integrity | System-Signal-Integrity | Analog-ADC | Analog-LDO | Digital-DV | System-Filters |

Tomasz Hemperek

SKILLS

Verilog |

AREA OF EXPERTISE

Digital-RTL |

Antonio Agripino

Master's student at UFCG. Work with Cadence tools. I work with AMS and digital circuits (using Verilog language) and analog layout as well.

SKILLS

Cadence Encounter | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Digital: Placement and Routing | Digital: Synthesis |

Michael Welling

SKILLS

C/C++ | Verilog | KiCAD |

AREA OF EXPERTISE

Business: PCB Manufacture | Circuits: Microcontrollers | Digital: Synthesis | System: FPGA Programming | System: PCB |

Yunzhe Li

MS IC Designer, focusing on imager design in deep submicron technologies

SKILLS

Cadence Virtuoso | Calibre | Diva | SKILL | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Sensors | Digital: RTL | Digital: Verification | System: FPGA Programming | System: PCB | System: Signal Integrity | System: Test Equipment |

Sebastián Guerrero

SKILLS

Analog CMOS Circuit | Analog/Digital Circuit Design | Python | Verilog |

AREA OF EXPERTISE

Analog-Amplifiers | Analog-Mixed Signal-DV |

Mohammed Nabeel

Learner for life

SKILLS

Perl | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | Digital: Synthesis | Digital: Verification | Miscellaneous: Cryptography | System: FPGA Programming |

Mahmoud Youssuf Ahmad

Graduate student of ECE department Ain Shams University, and Currently Master Student of ECE department Cairo University with major of Electronics design.

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eagle CAD | Matlab | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | CAD: Scripting | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning | System: FPGA Programming |

Vladislav Kulikov

SKILLS

C | Electronics Engineering | Verilog |

AREA OF EXPERTISE

System: FPGA Programming |

Sean Cross

SKILLS

C/C++ | Perl | Python | Verilog |

AREA OF EXPERTISE

Miscellaneous: Neural Networks | System: FPGA Programming | System: PCB | System: Quality Assurance | System: Test Programming |

Federico Paredes

Digital designer experienced in high-speed ASICs for optical/copper transceivers, including DSPs, error correction and SoC support.

SKILLS

C/C++ | Cadence Encounter | Matlab | Octave | Python | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Communication | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Kevin André Castillo Andrade

Electrical Engineer student

SKILLS

Analog IC Design | C/C++ | Matlab | Verilog |

AREA OF EXPERTISE

Analog |

Karan Shah

SKILLS

Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Modeling | Analog: Simulation | Analog: Verification |

Luis Enrique Rodriguez Mecca

Analog IC designer with knowledge and experience related to topics in analogl full-custom IC design such as current mirrors, single and differential amplifiers, bandgaps circuits and charge pump.

SKILLS

Analog CMOS Circuit | Analog IC Design | Matlab | Python | Verilog |

AREA OF EXPERTISE

Analog IC | Analog-Amplifiers | Analog-Layout |

Stephan Kanthak

SKILLS

C/C++ | ngspice | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Miscellaneous: Neural Networks |

ANTON BABUSHKIN

SKILLS

Verilog |

AREA OF EXPERTISE

ASIC Design/Verification |

Nambi

SKILLS

C/C++ | ngspice | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Verification | Business: Design Services | CAD: Tool Development | Digital: Verification | SoC: Verification |

Amr Walid

Experienced Mixed Signal Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Data Conversion, Analog Circuit Design, CMOS and Mixed Signal. Strong engineering professional with a Master's degree focused in Electronics Engineering from Ain Shams University.

SKILLS

Analog Circuit Design | Cadence Virtuoso | Matlab | PCB Design | verilog A |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Business: Packaging | Business: PCB Manufacture | Circuits: Sensors | System: Packaging | System: PCB | System: Test Equipment |

Muhammad Awais Bin Altaf

SKILLS

Cadence Virtuoso | Calibre | Matlab | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Sensors | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Mehdi Abderezai

Analog Mixed Signal IC Designer

SKILLS

Cadence Virtuoso | Calibre | System Verilog | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification |

Carlos Stahr

SKILLS

Verilog |

AREA OF EXPERTISE

Business: Design Services |

Ahmed Khalaf

SKILLS

C/C++ | Software Developer | Verilog |

AREA OF EXPERTISE

Digital-RTL |

Mathias Mahn

SKILLS

Analog/Digital Circuit Design | Scilab | Verilog |

AREA OF EXPERTISE

Analog-Layout | ASIC Design/Verification | Analog-ADC |

MOUSTAFA KHAIRY ABDELGALIL

SoC Design Enginner

SKILLS

Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Cryptography | Digital-RTL |

Clifford Wolf

Author of Yosys, IceStorm, PicoRV32, and other Open Source things

SKILLS

C/C++ | Circuit Design | Python | Software Developer | Verilog |

AREA OF EXPERTISE

ASIC Design/Verification | Automatic Circuit Design | CAD-Dev | CAD-Scripts | Design Automation | Digital-DV | Digital-RTL | Evolutionary algorithm | signal processing |

Marco Merlin

Electronics Engineer with 10 years experience in microelectronics and research. Familiar with CMOS integrated circuits design, wireless communication systems, programming and lab environment, I am comfortable working for worldwide semiconductors firms. Passionate for high-tech and music, advocate for teamwork and collective intelligence to support a strong problem-solving methodology, I am curious, self-motivated, addicted to learning and re-shaping the new technologies I am exposed to. During my workday I aspire to address "real-life problems", hopefully continuing to develop my multi-disciplinary skills as a means for technical and personal enrichment.

SKILLS

C/C++ | Cadence Virtuoso | Eagle CAD | Matlab | Octave | Python | SKILL | System Verilog | Verilog | VHDL | wifi | bluetooth | LTE |

AREA OF EXPERTISE

Analog: Verification | Circuits: Communication | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Neural Networks | SoC: Verification | System: PCB | System: Test Equipment | System: Test Programming |

Nishant Pani

SKILLS

Verilog |

AREA OF EXPERTISE

SOC-DV |

Jose T. de Sousa

José T. de Sousa holds a PhD degree from Imperial College London (1998) and has been a university lecturer and researcher at Lisbon University (1999-present). He holds 4 international patents, is co-author of one book, and was General Chair of the Field Programmable Logic and Applications Conference in 2013. Dr. de Sousa has published more than 70 technical papers in international journals and conferences. He was co-founder and CEO of Coreworks, a semiconductor intellectual property company, which he ran from 2001 to 2013. His specialties are digital circuit design, hardware/software architecture, technical team management and semiconductor IP marketing and sales.

SKILLS

C/C++ | Cadence Encounter | Leadership | Matlab | Octave | Python | Software Developer | System Verilog | System-C | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Business: Design Services | Business: Management | Business: Marketing | Business: Packaging | Business: Patents | Business: Public Relations | Business: Sales | CAD: Scripting |

Caio Alonso da Costa

SKILLS

C/C++ | Cadence Encounter | Matlab | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL | Digital: Synthesis | Digital: Verification |

AGhani

Associate Professor (Electrical and Electronic Engineering) Implantable chip design Low power sensors

SKILLS

Cadence Encounter | Cadence Virtuoso | Leadership | Matlab | SPICE Opus | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Sensors | Digital: Placement and Routing | Digital: RTL | System: Chip Editing | System: FPGA Programming |

David Ward

Circuit Designer

SKILLS

Analog CMOS Circuit | Analog | Analog IC Design | Analog/Digital Circuit Design | Circuit Design | Python | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog | Analog IC | Analog IC Design | Analog-Amplifiers | Analog-Layout | Analog-Mixed Signal-DV | Analog-Modeling | Analog-Simulation | ASIC Design/Verification |

Niels Moseley

SKILLS

C/C++ | Cadence Encounter | DSP | Matlab | Python | Software Developer | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Digital: RTL | System: FPGA Programming |

Leonel ACUNHA GUIMARAES

SKILLS

Cadence Virtuoso | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Layout | CAD: Tool Development | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: Test Programming |

Chanaka Ashan Ganewattha

SKILLS

C/C++ | Eagle CAD | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Simulation | Circuits: Microcontrollers | Circuits: Signal Processing | System: Power Integrity | System: Signal Integrity |

Botond Sandor Kirei

SKILLS

C/C++ | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Circuits: Filters | Circuits: Signal Processing | Digital: RTL |

Shimon Hempling

SKILLS

Magic CAD | Python | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Ping-Liang

SKILLS

Cadence Virtuoso | Matlab | Perl | Python | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Analog: Design |

Caspar van VRoonhoven

>10 years of experience in precision analog and sensor interface IC design.

SKILLS

C/C++ | Cadence Virtuoso | Leadership | Python | SKILL | Spectre | Verilog | Precision | Verilog-AMS | ADCs | Sensors | Reference circuits |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Sensors |

Staf Verhaegen

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | Python | SKILL | Software Developer | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Open Source | SRAM | Standard Cells | Lithography |

Steve Hoover

EDA Founder

SKILLS

Circuit Design | Software Developer | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Design Automation | Digital-RTL |

Sethu Raman

SKILLS

Analog CMOS Circuit | Analog | Analog IC Design | Analog/Digital Circuit Design | Circuit Design | Noob | Perl | Verilog |

AREA OF EXPERTISE

Analog | Analog IC | Analog IC Design | Analog-Modeling | Analog-Simulation | Digital-RTL |

Driss Ben Zoubeir

SKILLS

Analog/Digital Circuit Design | C/C++ | Verilog |

AREA OF EXPERTISE

Analog-Modeling | Analog-Simulation | Digital-DV |

Islam Hussein

SKILLS

Cadence Virtuoso | Calibre | Matlab | SKILL | Verilog |

AREA OF EXPERTISE

Analog: Design |

Hajime Suzuki

SKILLS

Analog CMOS Circuit | Analog IC Design | Matlab | Python | Verilog |

AREA OF EXPERTISE

Analog IC Design |

Yao Ming Kuo

Hardware design engineer

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Python | Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Wessam Ahmed

Senior ASIC Design Engineer

SKILLS

Analog/Digital Circuit Design | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Digital-DFT | Digital-DV | Digital-RTL |

Max Fil

SKILLS

C/C++ | Matlab | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

ASIC Design/Verification | Communication and Signal Processing | Digital-RTL | System-DSP |

Alfonso Chacon-Rodriguez

Professor in Electronics Engineering with a PhD. in VLSI (Universidad Nacional de Mar del Plata). Expertise in digital RTL and physical design. Experience in FPGA RTL and HLS design for heterogeneous computing. Knowledge in sub-threshold analog design. Fiction writer (National Literature Award for Novel, 2011, Costa Rica)

SKILLS

Calibre | Eldo | Electric CAD | Matlab | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis |

Mohamed Khairy Bahry

I have more than five years’ experience in electronics integrated circuits industry. I have been involved in more than six silicon runs which were all successful and meeting expectations.

SKILLS

Analog | Analog CMOS Circuit | Analog IC Design | Analog/Digital Circuit Design | Circuit Design | Matlab | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog | Analog IC | Analog IC Design | Analog-Amplifiers | Analog-Layout | Analog-LDO | Analog-Mixed Signal-DV | Analog-Modeling | Analog-Simulation | Analog-Verification | ASIC Design/Verification |

Pushkaraksha K M

Physical design engineer with strong expertise in CAD and low power methodologies

SKILLS

Cadence Encounter | Python | Tcl/Tk | Verilog |

AREA OF EXPERTISE

CAD: Tool Development | Digital: Placement and Routing | SoC: Floorplanning |

Ahmed Agiza

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: Synthesis |

ardencaple

Semiconductor professional with 40 years experience. I act as a technical consultant, design consultant, or architect for SoCs, embedded systems etc.

SKILLS

C/C++ | Leadership | Python | Verilog | VHDL | DC | PrimeTime |

AREA OF EXPERTISE

CAD: Scripting | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: Fabrication Process | System: FPGA Programming | Digital audio | IoT | Soc | Mixed Signal |

Bharath Shashidhar

SKILLS

System Verilog | Verilog |

AREA OF EXPERTISE

Digital: RTL |

Jacob Rast

SKILLS

Analog/Digital Circuit Design | C/C++ | Matlab | Python | Verilog |

AREA OF EXPERTISE

Analog |

Travis Ayres

SKILLS

Verilog |

AREA OF EXPERTISE

Digital-RTL |

Mohamed Kassem

We are building a community of OSHW Product Creators. Our focused mission is to simplify the process of smart product creation and making it available to everyone. We believe in Open Source Hardware as the foundation for addressing the massive and divergent forms and features of the new connected world.

SKILLS

Analog/Digital Circuit Design | Scilab | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog IC Design | ASIC Design/Verification |

Waleed Madany

Integrated Circuit designer

SKILLS

Analog/Digital Circuit Design | C/C++ | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog IC Design |

Mustafa Sami

SKILLS

Cadence Virtuoso | Calibre | Matlab | Python | Spectre | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student | Analog: Design | Analog: Layout | Analog: Simulation | Circuits: Communication | Circuits: Filters | Circuits: Power Management |

Don Morgan

SKILLS

C/C++ | Python | Scilab | Verilog | VHDL |

AREA OF EXPERTISE

System: FPGA Programming |

Paulo Roberto Bueno de Carvalho

Paulo Roberto B. de Carvalho is a Hardware and Digital IC Design Engineer with 6-years experience in microelectronic area in Digital IC Design, with specialization in RTL design optimization for area and power reduction, Verification and Physical Implementation flow. He has 10-years experience in Application Engineering, technical consultant and semiconductors manufacture processes. He received his bachelor degree in materials, processes and electronic components technology at Faculdade de Tecnologia de Sao Paulo (FATEC-SP) in 2006. In 2011, he joined the Brazillian Federal Government IC Brazil Program of the Ministry of Science, Technology and Innovation (MCTI), trained in Digital Systems Design area. He received his Master of Science degree in Electric Engineering with specialization in Microelectronic area on Integrated Systems Laboratory at Electrical Engineering Department of Polytechnic School of University of Sao Paulo in 2016.

SKILLS

C/C++ | Cadence Encounter | Python | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Circuits: Communication | Circuits: Filters | Circuits: Signal Processing | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Floorplanning | SoC: Verification | System: FPGA Programming | System: PCB |

Marco António da Mota Carvalho Silva Pereira

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Spectre | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design |

Hossam Hassan

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Matlab | Python | System Verilog | System-C | Verilog |

AREA OF EXPERTISE

Academic: Research | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | Circuits: Microcontrollers | Circuits: Sensors | Circuits: Signal Processing | Digital: RTL | Digital: Synthesis | Digital: Verification | SoC: Verification | System: FPGA Programming | System: PCB |

Bob Ledzius

35 years mixed signal SoC, ASIC, and FPGA design and management experience. Concertal provides rapid functional IP integration using proprietary System Design Automation technology that includes delivery of RTOS capable fabric that supports loosely coupled HW operation including IP NbC (Network beyond the Chip). IP areas of expertise include common interfaces, data converters, modulators, digital filters, DSP, processors, FSM, and other custom specified functionality.

SKILLS

C/C++ | Leadership | Matlab | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Business: Design Services | Business: Management | Business: Patents | CAD: Scripting | CAD: Tool Development | Circuits: Filters | Circuits: Microcontrollers | Circuits: Signal Processing | Digital: RTL | Digital: Verification | Miscellaneous: Cryptography | SoC: Verification | System: FPGA Programming | System: PCB |

Rajanarender Suram

SKILLS

Cadence Virtuoso | Leadership | Spectre | Verilog |

AREA OF EXPERTISE

Analog: Design |

Pascal Buchschacher

designing mixed-mode ASICs since 1986 :-)

SKILLS

Cadence Virtuoso | Leadership | Matlab | Spectre | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Modeling | Analog: Simulation | Analog: Verification | SoC: Verification |

Ernesto Conde

Electrical engineer with over 7 years of experience in the semiconductor industry. Working experience in Analog IC Design, Silicon/FPGA Lab bring-up and testing, FPGA Prototyping/Emulation & ASIC/SoC Design,

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | ngspice | Python | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Analog: Design | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | System: FPGA Programming |

PEER MOHAMED

SKILLS

Analog CMOS Circuit | Analog IC Design | Analog/Digital Circuit Design | Matlab | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Analog IC Design | Analog-Modeling | Analog-Simulation | ASIC Design/Verification | Automatic Circuit Design | Communication and Signal Processing | Design Automation | Digital-DFT | signal processing | Analog-ADC | Digital-RTL |

Hasan Mohamed

SKILLS

C/C++ | Python | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Digital: RTL | Digital: Synthesis | Miscellaneous: Neural Networks | System: FPGA Programming |

ِAhmed

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Eldo | Matlab | Spectre | System Verilog | Tcl/Tk | Verilog | VHDL | vb |

AREA OF EXPERTISE

Academic: Research | CAD: Tool Development |

Salvatore M. Cherchi

SKILLS

C/C++ | Eagle CAD | Electric CAD | Matlab | ngspice | Python | System Verilog |

AREA OF EXPERTISE

Analog: Design | Analog: Layout | Analog: Modeling | Business: Design Services | Circuits: Communication | Circuits: Memory | Circuits: Signal Processing | Miscellaneous: Cryptography | SoC: ESD | SoC: Floorplanning | System: Fabrication Process | System: Power Integrity | System: Signal Integrity |

Youstina Maher

SKILLS

System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

CAD: Scripting | Digital: Synthesis |

Thomas Dye

SKILLS

C/C++ | ngspice | Verilog |

AREA OF EXPERTISE

Analog: Design |

HALIM

Lecturer UiTM

SKILLS

System Verilog | Tanner L-Edit | Verilog |

AREA OF EXPERTISE

Academic: Teaching | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | SoC: Floorplanning |

Balaraju

iam presently working as an Soc verification Engineer

SKILLS

Verilog |

AREA OF EXPERTISE

SOC-DV |

Mahmoud Abdelgawad

SKILLS

C/C++ | Cadence Encounter | Cadence Virtuoso | Calibre | Matlab | Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

Academic: Research | Digital: DFT | Digital: RTL | Digital: Synthesis | Digital: Verification |

Mostafa Elbediwy

Teaching assistant for ASIC/FPGA and digital ICs courses.

SKILLS

C/C++ | Cadence Virtuoso | Calibre | Matlab | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Digital: DFT | Digital: Placement and Routing | Digital: RTL | Digital: Synthesis | Digital: Verification |

Martin Simlastik

digital ASIC designer with 10+ yrs experience

SKILLS

Electric CAD | Matlab | Perl | Python | Software Developer | System Verilog | Tcl/Tk | Verilog | VHDL |

AREA OF EXPERTISE

IC |

Giri Krishna

Electronics Engineer

SKILLS

Analog/Digital Circuit Design | Verilog | VLSI/ASIC and SoC Development |

AREA OF EXPERTISE

Digital-RTL |

Mostafa El Naggar

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Digital: RTL | Digital: Synthesis |

Akram Selim

SKILLS

Verilog | VHDL |

AREA OF EXPERTISE

Digital: RTL |

Mahadev Shiva Bhat

I am enthusiastic student in SoC designing

SKILLS

C/C++ | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Salma Hasan

SKILLS

C/C++ | Cadence Virtuoso | Matlab | System Verilog | Verilog | VHDL |

AREA OF EXPERTISE

Academic: Student |

Netsanet gebeyehu

Analog/RF/Digital design manager

SKILLS

Cadence Virtuoso | Calibre | Matlab | Verilog |

AREA OF EXPERTISE

Analog: Design | Digital: RTL |

Thiago Coura

SKILLS

Python | System Verilog | Tcl/Tk | Verilog |

AREA OF EXPERTISE

SoC: Verification |

Sandeep Gunturi

SKILLS

C/C++ | Cadence Virtuoso | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Angel Diéguez

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | Diva | Leadership | Verilog |

AREA OF EXPERTISE

Academic: Research | Academic: Teaching | Analog: Design | Analog: Layout | Analog: Simulation | Analog: Verification | Business: Management |

Gangadhar Yedida

I am studying Electronics and communication engineering (Integrated MTech) in International institute of information technology, Bangalore . I want to get access to tools for course project .

SKILLS

Verilog |

AREA OF EXPERTISE

System: Fabrication Process |

Mahruz Aziz

SKILLS

Verilog |

AREA OF EXPERTISE

Digital: Verification |

勤一刘

SKILLS

C/C++ | Perl | System-C | Verilog |

AREA OF EXPERTISE

Digital: Verification |

Viraj Bharadwaj Korede

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Octave | Python | Verilog |

AREA OF EXPERTISE

Academic: Student |

Jhalak Sharma

SKILLS

Cadence Virtuoso | Matlab | Python | Verilog |

AREA OF EXPERTISE

Academic: Research |

kowtarapu chaitanya

SKILLS

C/C++ | Cadence Virtuoso | System Verilog | Verilog | ltspice |

AREA OF EXPERTISE

Analog: Design | SoC: Verification |

Avinash k Patil

SKILLS

C/C++ | Verilog |

AREA OF EXPERTISE

Academic: Student |

Monika Sidde

Right now, I am working on physical design of ASIC.

SKILLS

C/C++ | Python | Verilog |

AREA OF EXPERTISE

Academic: Research |

Sahithi Meenakshi

SKILLS

Cadence Virtuoso | Verilog |

AREA OF EXPERTISE

Academic: Student |

Lalith Kota

SKILLS

C/C++ | Cadence Virtuoso | Matlab | Octave | Python | Software Developer | Verilog |

AREA OF EXPERTISE

Academic: Student |

Saroja V.S.

I am A professor

SKILLS

Cadence Encounter | Cadence Virtuoso | Calibre | System Verilog | Verilog |

AREA OF EXPERTISE

Academic: Research |

Rakesh Singanahalli

Hello I am Rakesh , I am pursuing my Under Graduation in Electronics and Communication Engineering at KLE Technological University, Hubballi. I am looking ahead work in Digital VLSI Domain. :D